Nexperia USA Inc. 74AXP1G00GSH

Overview

74AXP1G00 from Nexperia is a single 2-input NAND gate logic IC with Schmitt-trigger inputs, operating across 0.7 V to 2.75 V supply, delivering 0.6 μA max ICC at 85 °C, 2.5 pF typical CPD at 1.2 V, and IOFF-enabled partial power-down protection. It serves as a low-power signal combiner in battery-powered sensor interfaces and voltage-level tolerant control paths.

For engineers reviewing the 74AXP1G00 datasheet, 74AXP1G00 pinout, 74AXP1G00 application, or 74AXP1G00 equivalent, key selection criteria include ultra-low static/dynamic power consumption, sub-1 V operation capability, Schmitt-trigger noise immunity, and IOFF-backed system-level power sequencing support.

Technical Context

This device implements a standard NAND Boolean function with hysteresis on both inputs (Schmitt-trigger), enabling robust operation with slow-rising signals and high noise margin. Its IOFF circuit actively disables output leakage when VCC = 0 V, preventing backflow current during partial power-down sequences.

It complies with JEDEC standards JESD8-12A.01 through JESD8-5A.01 for multiple voltage domains and meets HBM ESD >2 kV and CDM >1000 V requirements. Input tolerance extends to 2.75 V regardless of VCC level, supporting mixed-voltage interfacing.

Key Specifications

Pinout & Package

XSON6 (SOT886/SOT1115/SOT1202) and X2SON5 (SOT1226-3) packages are available; all variants use leadless, ultra-thin construction with body heights ≤0.5 mm and footprint areas <1.5 mm². SOT886 measures 1.0 × 1.45 × 0.5 mm; SOT1226-3 measures 0.8 × 0.8 × 0.32 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NAND gate applications.

Compared with 74LVC1G00GV and SN74LVC1G00DBVR, the 74AXP1G00 uniquely supports sub-1 V operation, Schmitt-trigger noise rejection, and IOFF-based power sequencing-making it the sole choice for energy-harvested sensors and multi-rail portable systems requiring safe power-state transitions.

Availability

74AXP1G00 is available at Aetrix Electronics and suitable for IoT sensor nodes, portable medical devices, and industrial control I/O expansion requiring stable component supply across extended temperature and ultra-low-power operation.

Supply support for 74AXP1G00 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-volume, high-reliability logic, discrete, and MOSFET solutions with leadership in energy-efficient technologies.

The AXP logic family targets ultra-low-power, wide-VCC applications including battery-powered edge devices and multi-voltage system interfaces, emphasizing sub-1 V functionality and robust power-state management.

FAQ

Does the 74AXP1G00 support true bidirectional level translation?

No. It is a unidirectional logic gate with voltage-tolerant inputs: inputs accept up to 2.75 V regardless of VCC, but output swing is rail-to-rail relative to the applied VCC. It can translate high-to-low voltage domains when used as a receiver, but not as a true bidirectional translator like dedicated level-shifters.

What is the minimum load capacitance for guaranteed timing performance?

The propagation delay specifications (e.g., 1.1–3.0 ns at 2.3–2.7 V) are characterized with CL = 0 pF per Table 10. Performance degrades linearly with increasing load; Fig. 7–11 show tpd vs. CL curves up to 140 pF. For <2 ns delay, keep CL ≤20 pF at VCC ≥2.3 V.

Can the n.c. pin on XSON6 packages be grounded or left floating?

The n.c. pin (Pin 5 in XSON6) is electrically isolated and must remain unconnected. Grounding or routing it may cause internal parasitic coupling or violate package thermal design rules. Datasheet Figure 4 explicitly labels it "n.c." with no internal connection.

How does IOFF behave when VCC is ramped slowly during power-up?

IOFF activates only when VCC falls below ~0.1 V (per Table 7 ΔIOFF condition). During slow ramp-up, the device transitions from IOFF-disabled to functional logic once VCC exceeds ~0.7 V. No undefined state or contention occurs - output remains high-impedance until VCC reaches operational threshold.