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Nexperia USA Inc. 74AXP1G02GN125

Part No.:
74AXP1G02GN125
Manufacturer:
Nexperia USA Inc.
Category:
Gates and Inverters
Package:
6-XFDFN
Datasheet:
Aetrix74AXP1G02GN125.pdf
Description:
IC GATE NOR
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:4,500

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Product details

Overview

74AXP1G02GN125 from Nexperia is a single 2-input NOR gate logic IC with Schmitt-trigger inputs, operating across 0.7 V to 2.75 V supply, delivering 2.0 ns typical propagation delay at 2.5 V, 0.5 pF input capacitance, and IOFF-enabled partial power-down capability for battery-sensitive systems.

For engineers reviewing the 74AXP1G02GN125 datasheet, 74AXP1G02GN125 pinout, 74AXP1G02GN125 application, or 74AXP1G02GN125 equivalent, key selection criteria include ultra-low static current (0.6 μA max at 85 °C), sub-1V operation support, Schmitt-trigger noise immunity, and XSON6 (SOT1115) package compatibility with high-density PCB layouts.

Technical Context

This device implements a single 2-input NOR function with Schmitt-trigger inputs that tolerate slow-rising/falling edges and provide hysteresis for robust noise rejection in noisy digital environments. Its IOFF circuit actively disables outputs during power-down to prevent backflow current.

It operates over -40 °C to +85 °C and supports JEDEC voltage standards across multiple VCC ranges (1.1–1.3 V, 1.4–1.6 V, etc.), enabling interoperability with mixed-voltage SoC interfaces and low-power microcontroller GPIOs.

Key Specifications

Parameter Value and Actual Design Meaning
Supply Voltage Range 0.7 V to 2.75 V - enables direct interface with sub-1V logic domains and multi-rail power architectures
Propagation Delay (tpd) 2.0 ns typical at VCC = 2.5 V - supports >200 MHz toggle rates in compact timing-critical paths
Input Capacitance (CI) 0.5 pF typical - minimizes loading on preceding drivers and preserves signal integrity in high-speed routing
Static Supply Current (ICC) 0.6 μA maximum at 85 °C - ensures nanoamp-level quiescent draw for always-on sensor nodes
IOFF Leakage Current ±0.5 μA max at VCC = 0 V - prevents cross-conduction and bus contention during partial power-down sequences
Input Hysteresis Enabled via Schmitt-trigger action - rejects <10% VCC noise spikes without external filtering components

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6 terminals, body size 0.9 × 1.0 × 0.35 mm - optimized for space-constrained portable and wearable PCBs.

Pin/Terminal Circuit Role Design Meaning
1 B Second logic input with Schmitt-trigger threshold; accepts up to 2.75 V regardless of VCC
2 A Primary logic input with Schmitt-trigger threshold; compatible with 1.2 V, 1.8 V, and 2.5 V I/O standards
3 GND Ground reference terminal; must be low-impedance for stable noise immunity and IOFF functionality
4 Y Inverted NOR output (A NOR B); drives capacitive loads ≤15 pF within specified tpd limits
5 n.c. No-connect terminal - left unconnected per design; not internally bonded or functional
6 VCC Power supply input; supports dynamic voltage scaling and brown-out tolerant operation down to 0.7 V

Key Features

Feature Design Value
Schmitt-trigger inputs Enables reliable switching with slow or noisy signals - eliminates need for external RC filters in industrial sensor interfaces
IOFF partial power-down Prevents backflow current when VCC = 0 V - critical for hot-swap, battery backup, and multi-domain power gating
Ultra-low ICC (0.6 μA max) Extends battery life in always-on IoT endpoints - measurable impact on years-long coin-cell operation
JEDEC-compliant voltage ranges Validated for 1.1–1.3 V, 1.4–1.6 V, 1.65–1.95 V, and 2.3–2.7 V operation - simplifies voltage translation in heterogeneous SoC designs
ESD robustness (HBM >2 kV, CDM >1000 V) Reduces handling sensitivity and field failure risk - meets IPC-7351B assembly reliability requirements

Applications

Industrial Sensor Interface Wearable Power Sequencing

Use Scenario: Level-shifting and debouncing push-button or reed-switch inputs in factory-floor sensors.

IC Role / Device Role / Timing Role: NOR gate performs active-low OR logic with Schmitt-trigger input conditioning to reject EMI-induced glitches.

Use Value: Eliminates external RC networks and reduces BOM count while maintaining >10 kV/m ESD immunity per IEC 61000-4-2.

Use Scenario: Controlling enable sequencing of BLE SoC, PMIC, and display driver in smartwatch firmware boot flow.

IC Role / Device Role / Timing Role: Generates synchronized power-good assertion using two independent reset sources feeding the NOR inputs.

Use Value: Ensures deterministic startup order with <2.5 ns skew between rails, avoiding latch-up during cold start.

Low-Power MCU GPIO Expansion USB-C Port Logic Arbitration

Use Scenario: Adding hardware-based interrupt combining for multiple environmental sensors connected to an ARM Cortex-M0+ MCU.

IC Role / Device Role / Timing Role: Single-gate NOR aggregates four sensor alert lines into one IRQ line, with Schmitt inputs tolerating slow analog comparator outputs.

Use Value: Reduces MCU wake-up latency by 3× versus software polling, while consuming <1 nW average power in sleep mode.

Use Scenario: Resolving CC1/CC2 orientation detection conflicts during USB-C plug insertion in portable docking stations.

IC Role / Device Role / Timing Role: NOR gate implements priority arbitration between dual-role port controllers to enforce host-peripheral role assignment.

Use Value: Guarantees <500 ns decision latency under 0.8 V VBUS conditions - meets USB Type-C specification timing budgets.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NOR gate applications.

Alternative Part Technical Difference Application Difference Selection Advice
74LVC1G02GW Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; no Schmitt inputs Requires ≥1.65 V supply; unsuitable for sub-1V domains or partial power-down systems Select only if interfacing with 3.3 V or 5 V logic and no power-gating is needed
SN74LVC1G02DBVR Same VCC range as 74AXP1G02GN125 but lacks Schmitt inputs; IOFF not implemented; SOT-23-5 package Higher susceptibility to noise on slow edges; incompatible with ultra-low-power shutdown modes Choose only when board space allows SOT-23 and system noise floor is controlled externally

Compared with 74LVC1G02GW and SN74LVC1G02DBVR, the 74AXP1G02GN125 uniquely combines sub-1V operation, Schmitt-trigger noise immunity, and IOFF power-down - making it the sole option for energy-harvesting sensor nodes and multi-rail wearables requiring guaranteed glitch-free logic at nanowatt quiescent power.

Availability

74AXP1G02GN125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable power sequencing, low-power MCU GPIO expansion, and USB-C port logic arbitration requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AXP1G02GN125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading global semiconductor expert in high-volume, high-reliability discrete, logic, and MOSFET devices, headquartered in Nijmegen, Netherlands, serving automotive, industrial, and consumer markets.

The 74AXP series targets ultra-low-power logic applications in battery-operated and energy-constrained systems, emphasizing sub-1V operation, nanoamp ICC, and robust IOFF behavior for modern mixed-signal SoC integration.

FAQ

Does 74AXP1G02GN125 support operation below 1.0 V?

Yes - it is fully specified from 0.7 V to 2.75 V, with validated propagation delay (11 ns typ), input thresholds, and IOFF functionality at 0.75 V. This enables direct use with energy-harvesting circuits and advanced-node MCUs operating in near-threshold mode.

What is the purpose of the n.c. pin (Pin 5) in the SOT1115 package?

Pin 5 is a no-connect terminal with no internal bond wire or silicon connection. It must remain unconnected on the PCB. Its presence maintains mechanical symmetry and thermal uniformity in the XSON6 footprint, aiding reflow yield and thermal dissipation consistency.

How does the IOFF feature behave when VCC is ramping or floating?

IOFF activates only when VCC is near 0 V (≤0.1 V). During VCC ramp-up or floating conditions, the output remains functional per the truth table. Backflow prevention is guaranteed only after full power removal - not during brown-out or undervoltage lockout transitions.

Can 74AXP1G02GN125 drive a 15 pF load within its 2.0 ns typical tpd spec?

No - the 2.0 ns typical propagation delay is measured at CL = 5 pF. At 15 pF, tpd increases to ~4.0 ns (per Fig. 7 at VCC = 2.5 V). For 15 pF loads, verify timing margins using the published CL vs. tpd curves in Figures 7–11.

74AXP1G02GN125 Specifications

Product attributes
Attribute value
Manufacturer:
Nexperia USA Inc.
Series:
74AXP
Package/Case:
6-XFDFN
Packaging:
Bulk
Product Status:
Not For New Designs
Logic Type:
NOR Gate
Number of Circuits:
1
Number of Inputs:
2
Features:
-
Voltage - Supply:
0.7V ~ 2.75V
Current - Quiescent (Max):
300 nA
Current - Output High, Low:
8mA, 8mA
Input Logic Level - Low:
0.7V
Input Logic Level - High:
1.6V
Max Propagation Delay @ V, Max CL:
2.8ns @ 2.5V, 5pF
Operating Temperature:
-40°C ~ 85°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
6-XSON (0.9x1)

74AXP1G02GN125 FAQ

1.How can I place an order for 74AXP1G02GN125 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AXP1G02GN125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AXP1G02GN125 reliable?

The price and inventory of 74AXP1G02GN125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AXP1G02GN125 is usually 5 days.

3.What payment methods are accepted for 74AXP1G02GN125?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AXP1G02GN125 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74AXP1G02GN125?

74AXP1G02GN125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74AXP1G02GN125 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AXP1G02GN125?

For technical support, including 74AXP1G02GN125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AXP1G02GN125 requirements.

6.How does Aetrix verify that 74AXP1G02GN125 is sourced from the original manufacturer or authorized distributors?

All 74AXP1G02GN125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AXP1G02GN125 meets industry standards.

7.What is the process for return or replacement of 74AXP1G02GN125?

All 74AXP1G02GN125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AXP1G02GN125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AXP1G02GN125 part is unused and in its original packaging.

Return procedure for 74AXP1G02GN125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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