Nexperia USA Inc. 74AXP1G02GS125

Overview

74AXP1G02GS125 from Nexperia is a single 2-input NOR gate logic IC with Schmitt-trigger inputs, operating across 0.7 V to 2.75 V supply, delivering 0.6 μA max ICC at 85 °C, 2.6 pF typical CPD at 1.2 V, and IOFF-enabled partial power-down protection. It serves as a low-power signal combiner or noise-immune level translator in battery-powered sensor interfaces and portable I/O expansion circuits.

For engineers reviewing the 74AXP1G02GS125 datasheet, 74AXP1G02GS125 pinout, 74AXP1G02GS125 application, or 74AXP1G02GS125 equivalent, key selection criteria include ultra-low static/dynamic power consumption, sub-1V operation capability, IOFF backflow prevention, and XSON6 package compatibility with high-density PCB layouts.

Technical Context

This device implements a single 2-input NOR function with Schmitt-trigger input thresholds-ensuring robust noise immunity against slow-rising signals-and supports full rail-to-rail input voltage tolerance up to 2.75 V independent of VCC. Its IOFF circuit actively disables outputs during power-down, blocking destructive backflow current when VCC = 0 V.

Dynamic performance is characterized by propagation delays ranging from 1.1 ns (VCC = 2.3–2.7 V) to 32 ns (VCC = 0.75–0.85 V), with input and output capacitances fixed at 0.5 pF and 1.0 pF respectively-enabling predictable timing in low-capacitance load environments.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm (SOT1202).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input NOR gate applications.

Compared with SN74LVC1G02DBVR and 74LVC1G02GW,125, the 74AXP1G02GS125 uniquely delivers sub-1V operation, Schmitt-trigger noise immunity, and IOFF protection-making it the sole choice for energy-harvesting nodes, wearables with intermittent power, and modular systems requiring safe live insertion.

Availability

74AXP1G02GS125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable I/O expansion, low-power wearable controllers, and automotive body control modules requiring stable component supply across extended temperature ranges and ultra-low power budgets.

Supply support for 74AXP1G02GS125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74AXP series targets ultra-low-power logic applications demanding sub-1V operation, minimal leakage, and robust noise immunity-designed specifically for battery-constrained and thermally sensitive embedded systems.

FAQ

What is the minimum supply voltage at which 74AXP1G02GS125 guarantees correct logic operation?

The device is fully specified from 0.7 V to 2.75 V per JEDEC standards. At VCC = 0.7 V, VIH is guaranteed ≥0.75×VCC (≥0.525 V) and VOL ≤0.275 V with 2 mA sink current-enabling reliable operation in energy-harvesting systems powered by single-cell LiFePO₄ or supercapacitors.

Does 74AXP1G02GS125 require external pull-up or pull-down resistors on unused inputs?

No. Unused inputs must be tied to VCC or GND-floating inputs are prohibited due to CMOS topology. Schmitt-trigger inputs eliminate need for external hysteresis components, but intentional floating violates Absolute Maximum Ratings and risks increased ICC or latch-up.

How does the IOFF feature behave when VCC is ramping during power-up or power-down sequences?

IOFF activates only when VCC falls below ~0.1 V. During ramping, the output remains functional until VCC crosses the IOFF threshold. For controlled sequencing, tie VCC to a supervisor IC that asserts reset before VCC drops below 0.1 V to avoid metastable output states.

Can 74AXP1G02GS125 drive a 50 pF capacitive load at 1.2 V supply?

At VCC = 1.2 V, tpd increases to ~4.3 ns (typ) with 15 pF load (Fig. 8). Driving 50 pF would extend delay beyond 10 ns and increase dynamic power disproportionately. For >20 pF loads, add a buffer stage or reduce trace length-this device is optimized for point-to-point routing with minimal stubs.