Nexperia USA Inc. 74AXP1G04GMH

Overview

74AXP1G04GMH from Nexperia is a single low-power inverting buffer with Schmitt-trigger inputs, designed for ultra-low-voltage logic interfacing in battery-powered and space-constrained systems. It operates across 0.7 V to 2.75 V supply, delivers 2.3 pF typical dynamic power dissipation at 1.2 V, supports partial power-down via IOFF, and is rated for -40 °C to +85 °C ambient operation.

For engineers reviewing the 74AXP1G04GMH datasheet, 74AXP1G04GMH pinout, 74AXP1G04GMH application, or 74AXP1G04GMH equivalent, key selection criteria include its sub-1V operation capability, 0.5 pF input capacitance, IOFF-enabled isolation during system sleep states, and XSON6 (SOT886) package compatibility with high-density PCB layouts.

Technical Context

This device implements a single-channel inverter with hysteresis on the input (Schmitt-trigger), enabling robust noise immunity and tolerance of slow-rising/falling signals in mixed-voltage or noisy digital environments. Its IOFF circuit actively disables output leakage when VCC = 0 V, preventing backflow current in partial power-down modes.

It meets JEDEC standards JESD8-12A.01 through JESD8-5A.01 across multiple voltage bands and achieves HBM ESD >2 kV and CDM >1000 V. Propagation delay ranges from 1.0 ns (VCC = 2.3–2.7 V) to 33 ns (VCC = 0.75–0.85 V), scaling predictably with supply and load capacitance.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; thermal padless; moisture sensitivity level MSL1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar inverter applications.

Compared with SN74LVC1G04DBVR and 74LVC1G14GW,125, the 74AXP1G04GMH uniquely supports true sub-1V logic operation and IOFF-based system-level power management-making it irreplaceable in energy-constrained, multi-rail embedded designs where voltage scalability and safe power sequencing are mandatory.

Availability

74AXP1G04GMH is available at Aetrix Electronics and suitable for IoT sensor nodes, wearable power sequencing, USB-C configuration detection, and industrial PLC digital input buffering requiring stable component supply across extended temperature and ultra-low-voltage conditions.

Supply support for 74AXP1G04GMH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET devices optimized for efficiency-critical applications in automotive, industrial, and mobile markets.

The 74AXP series targets ultra-low-power logic interfacing in battery-operated and energy-sensitive systems, emphasizing sub-1V operation, minimal dynamic/static power, and robust IO behavior under partial power-down.

FAQ

What is the minimum supply voltage at which 74AXP1G04GMH guarantees functional operation?

The device is fully specified from 0.7 V to 2.75 V per JEDEC standards. At 0.7 V, propagation delay is 33 ns (max), input thresholds scale proportionally (VIH = 0.75×VCC), and output drive remains functional at ±20 μA. Operation below 0.7 V is not characterized or guaranteed.

Does 74AXP1G04GMH require external pull-up or pull-down resistors on unused pins?

No. Pins 1 and 5 are internally unconnected (n.c.) and must be left floating per datasheet guidance. Neither pin may be tied to VCC, GND, or any signal - doing so violates the XSON6 layout specification and risks electrical overstress or parametric shift.

How does the IOFF feature behave when VCC is ramping during power-up or power-down?

IOFF activates automatically when VCC drops below ~0.2 V and remains active until VCC exceeds ~0.4 V. During this transition window, output Y is high-impedance with ≤±0.1 μA leakage, preventing backflow even if A or Y are biased externally - confirmed by JESD78 latch-up testing and dynamic IOFF characterization.

Can 74AXP1G04GMH drive a 50 pF capacitive load while maintaining timing specifications?

Yes - propagation delay increases predictably with load capacitance. At VCC = 2.5 V, tpd rises from 2.0 ns (CL = 0 pF) to ~4.1 ns (CL = 50 pF), remaining within datasheet limits. The 1.0 pF typical CO and low-output-impedance design ensure stable edge rates without overshoot exceeding 10% of VCC.