Nexperia USA Inc. 74AXP1G04GSH

Overview

74AXP1G04GSH from Nexperia is a single low-power inverting buffer with Schmitt-trigger inputs, designed for signal conditioning and noise-immune logic level inversion in ultra-low-voltage systems. It operates across 0.7 V to 2.75 V supply, delivers <2.3 pF dynamic power dissipation at 1.2 V, supports IOFF partial power-down, and is specified from –40 °C to +85 °C for portable and battery-powered sensor interfaces.

For engineers reviewing the 74AXP1G04GSH datasheet, 74AXP1G04GSH pinout, 74AXP1G04GSH application, or 74AXP1G04GSH equivalent, key selection criteria include its sub-1 V operation capability, 0.5 pF input capacitance, IOFF-enabled system-level power gating, and compatibility with JEDEC voltage standards JESD8-12A.01 through JESD8-5A.01.

Technical Context

This device implements a single-channel inverter with Schmitt-trigger input thresholds-ensuring robust switching against slow-rising or noisy signals-and integrates an IOFF circuit that disables output leakage when VCC = 0 V. Its logic diagram confirms true inverting behavior (L→H, H→L) with no internal feedback or latch functionality.

Designed for multi-rail mixed-signal environments, it accepts input voltages up to 2.75 V independent of VCC and maintains defined logic states across its full 0.7–2.75 V operating range, enabling interoperability between 0.8 V, 1.2 V, 1.8 V, and 2.5 V domains without level shifters.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886), 6-terminal, no leads, body dimensions 1.0 × 1.45 × 0.5 mm; thermal pad not present; pin 1 index located below marking code in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar inverting buffer applications.

Compared with SN74LVC1G04DBVR and 74LVC1G14GW, the 74AXP1G04GSH uniquely combines sub-1 V operation, IOFF, and Schmitt-trigger input in one die-making it the sole choice for ultra-low-power, multi-rail, noise-prone applications where supply sequencing and signal integrity are co-constrained.

Availability

74AXP1G04GSH is available at Aetrix Electronics and suitable for IoT sensor nodes, wearable power sequencing, industrial timer reset circuits, and USB-C configuration detection requiring stable component supply across extended temperature and ultra-low-voltage conditions.

Supply support for 74AXP1G04GSH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The AXP logic family targets ultra-low-power, multi-voltage digital interface applications-designed specifically for energy-constrained systems requiring sub-1 V operation, IOFF, and robust noise immunity without performance trade-offs.

FAQ

Can 74AXP1G04GSH operate with VCC = 0 V while inputs are driven?

Yes-the IOFF circuitry actively disables the output and limits input-to-output leakage to <0.01 μA when VCC = 0 V, even if input pins are biased to up to 2.75 V. This allows safe hot-insertion and partial power-down scenarios without damaging upstream drivers or causing bus contention.

What is the minimum valid VCC for guaranteed logic operation?

The device is fully specified from VCC = 0.7 V, with static and dynamic parameters validated across this range. At 0.7 V, VIH is 0.75×VCC (≥0.525 V), VIL is 0.25×VCC (≤0.175 V), and tPD remains within 33 ns (typical 11 ns), enabling functional use in energy-harvesting and near-threshold computing systems.

Does the Schmitt-trigger input have fixed or VCC-scaled thresholds?

Thresholds are VCC-scaled: typical VIH = 0.65×VCC and VIL = 0.35×VCC over 1.1–1.95 V, and VIH = 1.6 V / VIL = 0.7 V at 2.3–2.7 V. This ensures consistent hysteresis margin (≈0.3×VCC) across operating voltages, unlike fixed-threshold Schmitt devices.

Is pin 1 location consistent across all XSON6 variants of 74AXP1G04?

Yes-per Figures 4 and 5 in the datasheet, pin 1 is always located in the lower-left corner beneath the marking code ("rC") for SOT886, SOT1115, and SOT1202 packages. For SOT1226-3 (X2SON5), pin 1 is similarly at the lower-left corner but with a 5-pin layout (VCC, A, GND, Y, n.c.).