Nexperia USA Inc. 74AXP1G08GSH

Overview

74AXP1G08GSH from Nexperia is a single 2-input AND gate logic IC with Schmitt-trigger inputs, operating across 0.7 V to 2.75 V supply, delivering ultra-low static current (0.6 μA max at 85 °C), input capacitance of 0.5 pF, and propagation delay as low as 1.1 ns at 2.7 V. It enables robust signal conditioning in battery-powered sensor interfaces and level-shifting I/O buffers.

For engineers reviewing the 74AXP1G08GSH datasheet, 74AXP1G08GSH pinout, 74AXP1G08GSH application, or 74AXP1G08GSH equivalent, key selection criteria include its IOFF-enabled partial power-down capability, JEDEC-compliant voltage scaling (JESD8-12A.01 through JESD8-5A.01), Schmitt-trigger noise immunity, and XSON6 package compatibility with high-density PCB layouts.

Technical Context

This device implements a single 2-input positive-logic AND function with Schmitt-trigger inputs that tolerate slow-rising/falling edges-critical for noisy or RC-filtered signals. Its IOFF circuit actively disables outputs during power-down, preventing backflow current when VCC = 0 V.

It supports multi-voltage domain interfacing via input tolerance up to 2.75 V independent of VCC, and meets stringent ESD robustness (HBM >2000 V, CDM >1000 V) and latch-up immunity (>100 mA per JESD78 Class II).

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 mm × 1.45 mm × 0.5 mm; wettable flank compatible; thermal pad optional.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input AND gate applications.

Compared with SN74LVC1G08DBVR and 74LVC1G08GW,125, the 74AXP1G08GSH uniquely delivers sub-1V operation, Schmitt-trigger noise rejection, and automatic IOFF shutdown-making it the sole option for ultra-low-power, multi-voltage, and hot-plug-safe AND logic in space-constrained designs.

Availability

74AXP1G08GSH is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable power management, multi-rail level translation, and hot-swappable module control requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AXP1G08GSH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, serving automotive, industrial, and consumer markets with scalable manufacturing and rigorous quality systems.

The 74AXP series targets ultra-low-power, wide-VCC logic applications-designed specifically for battery-operated, multi-voltage, and partial-power-down systems where traditional 74LVC or 74AUP families fall short in voltage range or isolation capability.

FAQ

Does 74AXP1G08GSH support true bidirectional voltage translation?

No. It is a unidirectional AND gate with voltage-tolerant inputs (up to 2.75 V) but output swing referenced only to its own VCC rail. For bidirectional level shifting, dedicated translators like NXSA5102 or TXB0108 are required. The 74AXP1G08GSH enables one-way logic combination across voltage domains when inputs exceed VCC.

What is the significance of the 'n.c.' pin in the XSON6 package?

Pin 5 is internally unconnected. It must not be soldered to VCC or signal traces. Best practice is to leave it floating or tie it to GND using a short trace to minimize stub capacitance and crosstalk-especially critical in high-speed or RF-proximate layouts where unused pins can act as antennas.

Can 74AXP1G08GSH drive a 50 pF load at 10 MHz while staying within its dynamic power budget?

Yes. At VCC = 1.2 V and fi = 10 MHz, dynamic power is PD = CPD × VCC² × fi = 2.4 pF × (1.2 V)² × 10 MHz ≈ 34.6 μW. With typical CO = 1.0 pF and negligible additional CL contribution, total power remains well below the 250 mW Ptot limit-even with 50 pF load, assuming driver strength suffices for required edge rate.

How does the IOFF feature behave when VCC ramps from 0 V to nominal?

IOFF activates automatically when VCC drops below ~0.2 V and deactivates once VCC exceeds ~0.4 V. During ramp-up, output remains in high-impedance state until VCC stabilizes above the functional threshold (~0.7 V), preventing glitches or contention on shared buses during power sequencing.