Nexperia USA Inc. 74AXP1G125GMH
- Part No.:
- 74AXP1G125GMH
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AXP1G125GMH.pdf
- Description:
- IC BUF NON-INVERT 2.75V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:10,000
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Product details
Overview
74AXP1G125 from Nexperia is a single low-power buffer/line driver with 3-state output, Schmitt-trigger inputs for noise immunity, IOFF partial power-down support, and operation across 0.7 V to 2.75 V supply. It delivers ultra-low static current (0.6 μA max at 85 °C), 0.5 pF input capacitance, and propagation delay as low as 1.1 ns at 2.7 V - enabling use in battery-powered I²C bus buffering and voltage-level translation between sub-1V logic domains.
For engineers reviewing the 74AXP1G125 datasheet, 74AXP1G125 pinout, 74AXP1G125 application, or 74AXP1G125 equivalent, key selection criteria include its wide VCC range (0.7–2.75 V), IOFF-enabled system power sequencing, Schmitt-trigger input hysteresis, and XSON6/X2SON5 package compatibility with high-density portable PCB layouts.
Technical Context
This device implements a single non-inverting buffer with active-low 3-state enable (OE), where input transitions are conditioned by Schmitt-trigger circuitry to tolerate slow-rising signals and suppress noise-induced glitches. The IOFF feature actively disables output leakage when VCC = 0 V, supporting hot-insertion and multi-rail power sequencing.
It operates across industrial temperature (−40 °C to +85 °C) and supports dynamic power scaling via CPD = 2.5 pF (typ. at 1.2 V), with propagation delays tightly specified from 1.1 ns (2.7 V) to 38 ns (0.75 V), enabling predictable timing in mixed-voltage signal routing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.7 V to 2.75 V - enables direct interface with 0.8 V, 1.2 V, 1.8 V, and 2.5 V logic families without level shifters. |
| ICC (max) | 0.6 μA at 85 °C - ensures negligible quiescent drain in always-on sensor nodes or backup power paths. |
| tpd (min) | 1.1 ns at VCC = 2.7 V - supports >300 MHz data throughput in high-speed control signaling. |
| CI / CO | 0.5 pF / 1.0 pF - minimizes capacitive loading on source drivers and preserves signal integrity in stubbed buses. |
| IOFF Leakage | ±0.1 μA max at VCC = 0 V - prevents backfeed current during partial power-down, protecting upstream supplies. |
| VIH/VIL Hysteresis | Input Schmitt-trigger with ~0.2×VCC hysteresis - rejects EMI and contact bounce in mechanical switch interfaces. |
| ESD Rating | HBM >2 kV, CDM >1000 V - withstands handling and board-level ESD events without external protection. |
Pinout & Package
XSON6 (SOT886/SOT1115/SOT1202) and X2SON5 (SOT1226-3) packages - both leadless, ultra-thin, and optimized for thermal performance and space-constrained layouts. SOT886 measures 1.0 × 1.45 × 0.5 mm; SOT1226-3 measures 0.8 × 0.8 × 0.32 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Active-low output enable | Drives Y to high-impedance when LOW; enables pass-through buffering when HIGH - critical for bus arbitration and shared-line control. |
| 2 (A) | Data input | Schmitt-triggered input accepts voltages up to 2.75 V independent of VCC - allows interfacing with higher-voltage peripherals. |
| 3 (GND) | Ground reference | 0 V return path for all internal logic and output stages; must be low-impedance to maintain noise immunity. |
| 4 (Y) | Buffered output | 3-state non-inverting output capable of sinking/sourcing ±20 mA - drives transmission lines or fan-out loads directly. |
| 5 (n.c.) | No-connect (XSON6 only) | Terminal not bonded internally - must remain unconnected to avoid parasitic coupling or mechanical stress. |
| 5/6 (VCC) | Supply voltage | Single-supply rail powering core logic and output stage; IOFF circuitry remains functional even when VCC = 0 V. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 0.7 V to 2.75 V supports integration into heterogeneous voltage domains (e.g., 0.8 V core + 1.8 V I/O). |
| IOFF partial power-down | Prevents damaging back-current flow when VCC is off - essential for PCIe slot hot-plug, USB-C PD negotiation, and modular systems. |
| Schmitt-trigger inputs | Input hysteresis improves noise margin by >100 mV at 1.2 V - eliminates false triggering from noisy sensors or long traces. |
| Ultra-low dynamic capacitance | CI = 0.5 pF and CO = 1.0 pF reduce switching energy and minimize signal distortion in high-frequency clock distribution. |
| Industrial temperature grade | Specified from −40 °C to +85 °C - suitable for automotive infotainment head units, industrial HMIs, and outdoor IoT gateways. |
Applications
| USB Type-C Port Controller Interface | I²C Bus Level Translation |
|---|---|
Use Scenario: Isolating and buffering I²C SDA/SCL lines between a 1.2 V microcontroller and 1.8 V sensor hub while maintaining bus arbitration. IC Role / Device Role / Timing Role: Non-inverting 3-state buffer with Schmitt-trigger inputs ensures clean signal edge regeneration and prevents cross-talk during multi-master contention. Use Value: Eliminates need for discrete MOSFET translators; IOFF prevents power-backfeed when sensor hub is powered down independently. |
Use Scenario: Driving USB-C CC line detection logic in portable chargers where VBUS presence must trigger a 0.8 V PMIC enable signal. IC Role / Device Role / Timing Role: Low-VCC buffer translates 5 V CC-line pulses to sub-1V logic thresholds with precise timing and no DC loading. Use Value: Schmitt-trigger input rejects noise from cable insertion transients; 0.5 pF CI avoids distorting fast CC pulse edges. |
| Low-Power Sensor Node Signal Conditioning | Hot-Swappable Module Presence Detection |
Use Scenario: Buffering analog switch control signals from an ultra-low-power MCU (0.9 V) to a 1.8 V analog front-end without level-shifter overhead. IC Role / Device Role / Timing Role: Single-gate buffer with IOFF ensures zero current draw during MCU sleep mode, preserving battery life. Use Value: ICC = 0.6 μA max at 85 °C extends shelf life and runtime in coin-cell-powered environmental monitors. |
Use Scenario: Detecting module insertion in telecom line cards using mechanical switch closure, where host FPGA runs at 1.2 V but switch contacts float near 3.3 V. IC Role / Device Role / Timing Role: Input-tolerant buffer clamps 3.3 V switch signals to safe levels for 1.2 V FPGA GPIO, with hysteresis preventing chatter. Use Value: VI up to 2.75 V and Schmitt action eliminate external resistive dividers and debounce firmware - reducing BOM and latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DBVR | Wider VCC (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; standard SO-5 package. | Requires external power sequencing controls; unsuitable for true partial power-down scenarios. | Select when interfacing legacy 3.3 V/5 V peripherals and board space permits larger SO-5 footprint. |
| 74LVC1G125GW,125 | Same XSON6 package; identical pinout; VCC range 1.65–5.5 V; lacks Schmitt-trigger inputs. | Higher minimum VCC excludes sub-1V operation; lower noise immunity increases susceptibility to EMI in dense layouts. | Choose only if operating strictly above 1.65 V and Schmitt-triggering is unnecessary for the signal source. |
Compared with SN74LVC1G125DBVR and 74LVC1G125GW,125, the 74AXP1G125 uniquely supports sub-1V operation, integrates IOFF for robust power sequencing, and provides Schmitt-trigger noise rejection - making it the sole choice for energy-harvesting nodes and multi-rail portable systems requiring guaranteed zero-backfeed and glitch-free enable control.
Availability
74AXP1G125 is available at Aetrix Electronics and suitable for USB-C port controllers, I²C bus translators, low-power sensor nodes, and hot-swappable module detection requiring stable component supply across industrial temperature and ultra-low power budgets.
Supply support for 74AXP1G125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions optimized for efficiency-critical applications.
The AXP logic family targets ultra-low-power, wide-VCC digital interfacing - designed specifically for battery-operated, space-constrained, and multi-voltage systems where static current, dynamic capacitance, and IOFF functionality are decisive.
FAQ
Does the 74AXP1G125 support operation below 0.7 V?
No. The absolute minimum recommended VCC is 0.7 V per Table 6. Operation below this violates the recommended operating conditions and may result in undefined logic states, increased propagation delay variation, or failure to meet ICC specifications. The device is not characterized or guaranteed for sub-0.7 V use.
Can the OE pin be left floating during normal operation?
No. OE is an active-low control input with no internal pull-up or pull-down. Leaving it floating risks indeterminate output state (Y may oscillate or settle unpredictably), violating the function table and potentially causing bus contention. OE must be driven HIGH (to VCC) or LOW (to GND) via a defined logic source or resistor network.
What is the maximum capacitive load the 74AXP1G125 can drive reliably?
The datasheet specifies timing parameters up to 50 pF load capacitance (Fig. 8–12). For reliable signal integrity and timing compliance, keep total load (including trace, probe, and downstream input capacitance) ≤50 pF. Exceeding this increases tpd and tt beyond guaranteed limits and may cause overshoot/undershoot exceeding 10% of VCC.
Is the 74AXP1G125 qualified for automotive applications?
No. This device is specified for industrial temperature (−40 °C to +85 °C) and carries no AEC-Q100 qualification. Nexperia explicitly states in Section 15 that non-automotive qualified products are "not suitable for automotive use" and lack testing per automotive reliability standards. Use only in consumer, industrial, or computing applications.
74AXP1G125GMH Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AXP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 0.7V ~ 2.75V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT886 (1.45x1)
74AXP1G125GMH FAQ
1.How can I place an order for 74AXP1G125GMH through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AXP1G125GMH on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AXP1G125GMH reliable?
The price and inventory of 74AXP1G125GMH are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AXP1G125GMH is usually 5 days.
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Once your 74AXP1G125GMH order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AXP1G125GMH?
For technical support, including 74AXP1G125GMH datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AXP1G125GMH requirements.
6.How does Aetrix verify that 74AXP1G125GMH is sourced from the original manufacturer or authorized distributors?
All 74AXP1G125GMH products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AXP1G125GMH meets industry standards.
7.What is the process for return or replacement of 74AXP1G125GMH?
All 74AXP1G125GMH units undergo pre-shipment inspection (PSI). If there is an issue with 74AXP1G125GMH, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AXP1G125GMH part is unused and in its original packaging.
Return procedure for 74AXP1G125GMH:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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