Nexperia USA Inc. 74AXP1G17GM125
- Part No.:
- 74AXP1G17GM125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AXP1G17GM125.pdf
- Description:
- 74AXP1G17GM - BUFFER, AXP SERIES
- Quantity:
- Payment:

- Shipping:

Inventory:4,250
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Product details
Overview
74AXP1G17GM125 from Nexperia is a single-channel low-power Schmitt trigger buffer in XSON6 (SOT886) package, designed for signal conditioning of slow-rising/noisy inputs in ultra-low-voltage systems. It operates from 0.7 V to 2.75 V, delivers 0.6 μA max ICC at 85 °C, features 0.5 pF input capacitance and IOFF partial power-down protection, and is used in battery-powered sensor interfaces and I²C bus level-shifting circuits.
For engineers reviewing the 74AXP1G17GM125 datasheet, 74AXP1G17GM125 pinout, 74AXP1G17GM125 application, or 74AXP1G17GM125 equivalent, key selection criteria include its sub-1-V operation capability, ±20 mA output drive, hysteresis voltage range (0.2–1.0 V), and guaranteed performance across –40 °C to +85 °C with JEDEC-compliant voltage standards.
Technical Context
This device implements a single Schmitt-triggered inverting buffer stage with asymmetric threshold hysteresis (VT+ and VT−) to reject noise on slow-transitioning signals. Its IOFF circuit actively disables outputs during power-down, preventing backflow current when VCC = 0 V while inputs/outputs remain biased up to 2.75 V.
It supports dynamic operation down to 0.7 V supply with propagation delays as low as 1.1 ns (VCC = 2.3–2.7 V, CL = 0 pF) and maintains <10% overshoot/undershoot. Input leakage remains ≤±0.5 μA over full temperature and voltage range, enabling reliable use in always-on monitoring nodes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 0.7 V to 2.75 V - enables direct interface with sub-1-V logic domains and energy-harvesting systems |
| Propagation Delay | 1.1 ns (min) at VCC = 2.3 V - ensures timing-critical signal cleanup without pipeline latency |
| Hysteresis Voltage | 0.2 V to 1.0 V - provides robust noise margin against EMI in industrial sensor front-ends |
| Input Capacitance | 0.5 pF (typical) - minimizes loading on high-impedance sources like crystal oscillators or capacitive sensors |
| IOFF Leakage | ±0.5 μA max at VCC = 0 V - prevents cross-talk and power loss in multi-rail partial-power-down architectures |
| Operating Temperature | –40 °C to +85 °C - qualified for industrial control, portable medical, and automotive body electronics |
| ESD Protection | HBM >2 kV, CDM >1000 V - withstands handling and board-level electrostatic events without shielding |
Pinout & Package
XSON6 plastic extremely thin small outline package (SOT886); no leads; 6 terminals; body dimensions 1.0 × 1.45 × 0.5 mm; thermal padless; moisture sensitivity level MSL1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | n.c. | No internal connection - electrically isolated; must be left floating or grounded per layout best practice |
| 2 | A | Data input - accepts voltages up to 2.75 V regardless of VCC; Schmitt-triggered for noise immunity |
| 3 | GND | Ground reference - common return path for supply and signal; requires low-inductance PCB connection |
| 4 | Y | Data output - rail-to-rail CMOS-compatible swing; drives loads up to ±20 mA with defined VOH/VOL |
| 5 | n.c. | No internal connection - electrically isolated; must be left floating or grounded per layout best practice |
| 6 | VCC | Supply voltage - powers internal logic; IOFF circuit activates automatically when VCC = 0 V |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low-voltage operation | Functional down to 0.7 V supply - supports next-generation sub-1-V SoC interconnects and energy harvesting nodes |
| IOFF partial power-down | Output disabled with <±0.5 μA leakage at VCC = 0 V - eliminates backfeed in hot-swap and multi-supply systems |
| Low dynamic power | CPD = 2.5 pF at VCC = 1.2 V - reduces switching power by >50% vs. standard AXP-series buffers at same frequency |
| High noise immunity | Input hysteresis ≥0.2 V across full VCC range - rejects burst noise and contact bounce in mechanical switch debouncing |
| JEDEC compliance | Validated per JESD8-12A.01 (1.1–1.3 V), JESD8-11A.01 (1.4–1.6 V), and JESD8-7A (1.65–1.95 V) - ensures interoperability with industry-standard logic families |
Applications
| Industrial Sensor Interface | I²C Bus Level Translation |
|---|---|
Use Scenario: Conditioning analog sensor outputs (e.g., thermistor, photoresistor) before ADC sampling in battery-powered data loggers. IC Role / Device Role / Timing Role: Schmitt trigger buffer cleans slow, noisy analog-derived digital edges and provides hysteresis to prevent metastability at threshold crossings. Use Value: Enables reliable edge detection at 0.8 V supply with <0.5 pF input loading, reducing system power by eliminating need for external op-amp conditioning stages. |
Use Scenario: Bridging 1.2 V microcontroller I²C pins to 1.8 V or 2.5 V peripheral devices in wearables and IoT edge nodes. IC Role / Device Role / Timing Role: Unidirectional level shifter with built-in hysteresis, ensuring clean SCL/SDA transitions despite voltage-domain mismatch and bus capacitance. Use Value: Eliminates external pull-up resistors on low-VCC side and sustains 400 kHz I²C timing with <1.3 ns propagation delay at 1.2 V, preserving bus timing margins. |
| USB-C CC Line Debounce | Low-Power Wake-Up Signal Conditioning |
Use Scenario: Debouncing USB-C configuration channel (CC) line signals in portable chargers and docking stations. IC Role / Device Role / Timing Role: Single-gate Schmitt trigger filters mechanical switch bounce and EMI-induced glitches on CC detection lines. Use Value: Guarantees glitch-free USB PD contract negotiation with <10% overshoot and 0.6 μA static current at 85 °C, extending standby battery life. |
Use Scenario: Converting weak, slow-rising wake-up signals (e.g., from motion sensor or RTC alarm) into clean MCU interrupt triggers. IC Role / Device Role / Timing Role: Low-leakage input buffer with IOFF isolation ensures zero current draw during deep sleep while accepting wake signals up to 2.75 V. Use Value: Reduces system wake-up latency to <2 ns and eliminates false triggers from RF coupling, verified across –40 °C to +85 °C. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Schmitt trigger buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G17DBVR | Wider VCC range (1.65–5.5 V); higher ICC (10 μA typ); no IOFF; 5-pin SOT-23 | Requires ≥1.65 V supply; unsuitable for sub-1-V systems or partial power-down designs | Select when interfacing with 3.3 V/5 V logic and IOFF is not required |
| 74LVC1G17GW,125 | Same XSON6 package; VCC = 1.65–5.5 V; no IOFF; CPD = 6.5 pF at 3.3 V | Lacks power-down isolation; higher dynamic power; incompatible with <1.65 V rails | Choose only for legacy 3.3 V designs where footprint compatibility is critical and IOFF is unnecessary |
Compared with SN74LVC1G17DBVR and 74LVC1G17GW,125, the 74AXP1G17GM125 uniquely supports sub-1-V operation and IOFF isolation-making it the sole option for energy-constrained, multi-rail systems requiring zero-power-state integrity.
Availability
74AXP1G17GM125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C level translation, USB-C CC line debounce, and low-power wake-up signal conditioning requiring stable component supply across extended temperature ranges.
Supply support for 74AXP1G17GM125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET devices optimized for efficiency-critical applications in automotive, industrial, and mobile markets.
The AXP logic family targets ultra-low-power, wide-supply-voltage digital signal conditioning-specifically engineered for battery-operated, energy-harvesting, and multi-rail embedded systems demanding sub-1-V functionality and IOFF safety.
FAQ
Can 74AXP1G17GM125 operate with VCC = 0.7 V while driving a 15 pF load?
Yes. At VCC = 0.7 V, the device delivers tPD ≤ 39 ns (max) into 15 pF, with VOH ≥ 0.69 V and VOL ≤ 0.1 V under specified conditions. Static current remains ≤0.6 μA at 85 °C, confirming full functionality at minimum supply.
What happens to the output when VCC = 0 V and input A = 2.75 V?
The IOFF circuit disables the output, clamping Y to high-impedance state with leakage ≤±0.5 μA. This prevents backflow current from the 2.75 V input into the unpowered device, satisfying JEDEC JESD78 Class II latch-up immunity requirements.
Is pin 1 marked on the 74AXP1G17GM125 package?
Yes. Per datasheet Figure 4 and Table 2, the pin 1 indicator is located on the lower-left corner of the device body, directly below the marking code "rJ", visible under magnification on the top surface of the XSON6 (SOT886) package.
How does hysteresis vary with supply voltage?
Hysteresis voltage (VH) scales with VCC: 0.06VCC–0.5VCC at 0.75–0.85 V, 0.1VCC–0.4VCC at 1.1–1.95 V, and 0.2–1.0 V at 2.3–2.7 V. This ensures consistent noise margin across all operating voltages without external resistor tuning.
74AXP1G17GM125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AXP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Not For New Designs
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- Schmitt Trigger
- Output Type:
- -
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 0.7V ~ 2.75V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (1.45x1)
74AXP1G17GM125 FAQ
1.How can I place an order for 74AXP1G17GM125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AXP1G17GM125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AXP1G17GM125 reliable?
The price and inventory of 74AXP1G17GM125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AXP1G17GM125 is usually 5 days.
3.What payment methods are accepted for 74AXP1G17GM125?
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Once your 74AXP1G17GM125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AXP1G17GM125?
For technical support, including 74AXP1G17GM125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AXP1G17GM125 requirements.
6.How does Aetrix verify that 74AXP1G17GM125 is sourced from the original manufacturer or authorized distributors?
All 74AXP1G17GM125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AXP1G17GM125 meets industry standards.
7.What is the process for return or replacement of 74AXP1G17GM125?
All 74AXP1G17GM125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AXP1G17GM125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AXP1G17GM125 part is unused and in its original packaging.
Return procedure for 74AXP1G17GM125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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