Nexperia USA Inc. 74AXP1G17GS125

Overview

74AXP1G17GS125 from Nexperia is a single-channel low-power Schmitt trigger buffer designed for signal conditioning in ultra-low-voltage digital systems. It converts slow-rising/falling input signals into clean, jitter-free CMOS-compatible outputs with hysteresis, operates across 0.7 V to 2.75 V supply, delivers <1.0 ns transition time at 2.7 V, and supports partial power-down via IOFF circuitry - used in battery-powered sensor interfaces and I²C bus level-shifting circuits.

For engineers reviewing the 74AXP1G17GS125 datasheet, 74AXP1G17GS125 pinout, 74AXP1G17GS125 application, or 74AXP1G17GS125 equivalent, key selection criteria include its sub-1 μA static ICC at 85 °C, 0.5 pF input capacitance, IOFF-enabled isolation during system sleep states, and compatibility with JEDEC voltage standards JESD8-12A.01 through JESD8-5A.01.

Technical Context

This device implements a single non-inverting Schmitt trigger stage with asymmetric hysteresis (VT+ and VT− varying by supply voltage), enabling robust noise rejection on noisy PCB traces or long cables. Its IOFF circuit actively disables output terminals when VCC = 0 V, blocking backflow current up to ±20 mA while maintaining input tolerance to 2.75 V independent of supply state.

Dynamic performance is optimized for low-capacitance loads: propagation delay ranges from 1.1 ns (min, 2.3–2.7 V) to 136 ns (max, −40 °C to +85 °C, 0.75–0.85 V), and transition time remains under 1.0 ns at 2.7 V with CL = 0 pF - critical for timing-critical edge detection in wearables and IoT node wake-up logic.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm (SOT1202). Pin 1 indicator located on lower left corner below marking code 'rJ'.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Schmitt trigger buffer applications.

Compared with SN74LVC1G17DBVR and 74LVC1G17GW,125, the 74AXP1G17GS125 uniquely combines sub-1 V operation, IOFF isolation, and 0.5 pF input capacitance - making it the sole option for ultra-low-power, multi-rail, and energy-constrained designs where leakage control and signal fidelity are co-critical.

Availability

74AXP1G17GS125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable device wake-up logic, and low-power microcontroller reset conditioning requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74AXP1G17GS125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, discrete, and MOSFET solutions with manufacturing rooted in process innovation and automotive-grade quality systems.

The 74AXP series targets ultra-low-power portable and battery-operated applications, delivering Schmitt trigger functionality with industry-leading static/dynamic power trade-offs and robust partial power-down capability.

FAQ

Can 74AXP1G17GS125 operate with VCC = 0.7 V and still meet timing specifications?

Yes - the device is fully characterized down to 0.7 V, with maximum propagation delay of 136 ns over −40 °C to +85 °C at this voltage. Static current remains ≤0.6 μA, and input hysteresis is maintained at 0.06×VCC to 0.5×VCC, ensuring reliable noise rejection even at minimum supply.

What happens to the Y output when VCC = 0 V and an input signal is applied to pin 2 (A)?

When VCC = 0 V, the IOFF circuit disables the output stage, forcing Y into high-impedance state regardless of A's voltage. Input A remains functional and tolerant up to 2.75 V, but no current flows into or out of Y - preventing backfeed into powered-down sections of the system.

Is the 74AXP1G17GS125 pin-compatible with other XSON6 Schmitt buffers like 74LVC1G17?

No - although both use SOT1202 (XSON6), 74AXP1G17GS125 has pins 1 and 5 marked 'n.c.', whereas 74LVC1G17 uses all six pins (including enable). Physical placement is identical, but PCB layout must isolate pins 1 and 5; direct replacement requires schematic and layout revision.

Does the 0.5 pF input capacitance specification include bond wire and pad parasitics?

Yes - the 0.5 pF typical value (Table 11, Dynamic Characteristics) is measured at the device terminals per JEDEC JESD22-B107, including die capacitance, bond wire, and pad contributions. Layout parasitics beyond the package must be added separately and typically contribute <0.1 pF in optimized RF-aware routing.