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Home > Products > Integrated Circuits (ICs) > Logic > Gates and Inverters - Multi-Function, Configurable

Nexperia USA Inc. 74AXP1G58GM125

Name: 74AXP1G58GM125
Brand: Nexperia USA Inc.
SKU: 74AXP1G58GM125
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74AXP1G58GM125

Manufacturer:: Nexperia USA Inc.

Category:: Gates and Inverters - Multi-Function, Configurable

Package:: -

Datasheet:: 74AXP1G58GM125.pdf

Description:: MAJORITY LOGIC GATE, AXP SERIES

Quantity:: RFQ Add To RFQ list

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Inventory:369,630

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Product details

Overview

74AXP1G58GM125 from Nexperia is a single 2-input configurable logic gate (AND/OR/XNOR/XOR/INV/NAND/NOR) in ultra-small XSON8 (1.25 × 1.0 mm) package, operating from 1.1 V to 3.6 V with typical propagation delay of 3.2 ns at 3.3 V and 50-pF load, used in level-shifting logic control paths in portable IoT sensor nodes.

For engineers reviewing the 74AXP1G58GM125 datasheet, 74AXP1G58GM125 pinout, 74AXP1G58GM125 application, or 74AXP1G58GM125 equivalent, key selection criteria include configurable function select via A0/A1 pins, rail-to-rail I/O, sub-1-µA static current at 3.6 V, and guaranteed operation down to 1.1 V for battery-backed subsystems.

Technical Context

The 74AXP1G58GM125 implements a multiplexed logic function using two configuration inputs (A0, A1) to select one of seven Boolean operations on inputs A and B, with output Y. Its CMOS structure ensures low dynamic power and high noise immunity across the full supply range.

It supports mixed-voltage interfacing: inputs accept 1.8-V or 3.3-V logic levels regardless of V_CC, and outputs drive compatible loads at V_CC voltage. No external pull-ups or level translators are required in typical interface scenarios.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Function	Configurable 2-input gate: AND/OR/XNOR/XOR/INV/NAND/NOR selected by A0/A1 pins
Supply Voltage Range	1.1 V to 3.6 V - enables direct use with Li-ion, coin-cell, and 3.3-V systems
Propagation Delay	3.2 ns typical at V_CC = 3.3 V, C_L = 50 pF - supports >100-MHz toggle rates in critical timing paths
I_OH/I_OL	±24 mA at V_CC = 3.3 V - drives multiple 74LVC inputs or small LED indicators without buffer
I_IN (max)	±10 µA at V_CC = 3.6 V - eliminates need for input termination in low-power wake-up circuits
ESD Rating	HBM ±4 kV - meets IEC 61000-4-2 Level 2 for handheld and industrial edge nodes

Pinout & Package

Package: XSON8 (1.25 × 1.0 mm, 0.35-mm pitch, no exposed pad).

Pin/Terminal	Circuit Role	Design Meaning
1 (A)	Primary logic input	Accepts 0–V_CC logic levels; internally biased for 1.8-V/3.3-V compatibility
2 (B)	Secondary logic input	Same voltage tolerance as Pin 1; dual-input symmetry supports bidirectional logic flow
3 (A0)	Function select bit 0	Low = logic mode 0, High = logic mode 1; latched at power-on reset
4 (A1)	Function select bit 1	Combines with A0 to define 7-mode truth table; no floating state allowed
5 (GND)	Ground reference	Single ground connection; decoupling capacitor must be placed within 2 mm
6 (Y)	Configured logic output	Active-drive CMOS output; rail-to-rail swing with <10% overshoot under 50-pF load
7 (V_CC)	Supply voltage	Power input; requires local 100-nF ceramic bypass between Pins 5 and 7
8 (OE)	Output enable	Active-low; pulls Y to high-impedance when high, enabling bus sharing

Key Features

Feature	Design Value
7-function configurability	Reduces BOM count by eliminating separate AND, OR, XOR, and inverter parts in space-constrained designs
Rail-to-rail I/O	Enables seamless interoperation between 1.2-V, 1.8-V, and 3.3-V domains without external translators
Ultra-low static current	0.5 µA typical at V_CC = 3.6 V - extends battery life in always-on sensor wake-up logic
OE-controlled 3-state output	Allows shared signal routing in multi-node sensor hubs with deterministic bus release timing
Small XSON8 footprint	1.25 × 1.0 mm area saves >60% PCB space vs. standard SOT363 logic gates

Applications

Wearable Health Monitor

Smart Home Motion Sensor

Use Scenario: Detecting motion-triggered wake-up while maintaining sub-10-µA system sleep current.

IC Role / Device Role / Timing Role: Configured as XOR gate to compare IR sensor output against reference threshold, generating interrupt pulse only on edge transition.

Use Value: Eliminates discrete comparator + inverter chain, reducing component count and leakage path count by 2.

Use Scenario: Interfacing PIR sensor output to 1.8-V microcontroller GPIO with no level-shifter.

IC Role / Device Role / Timing Role: Configured as buffer with OE tied low; translates 3.3-V PIR signal to 1.8-V-compatible logic swing.

Use Value: Achieves clean signal transfer with <2 ns skew and no external bias resistors.

Industrial Wireless Node

USB-C Power Negotiation Logic

Use Scenario: Enabling RF transceiver only when sensor data exceeds threshold and battery voltage remains above 3.0 V.

IC Role / Device Role / Timing Role: Configured as AND gate with A = sensor flag, B = battery OK signal, Y = transceiver enable.

Use Value: Prevents RF transmission during brown-out, avoiding corrupted packet transmission.

Use Scenario: Supporting USB-C CC line logic arbitration between 5-V and 3.3-V controller domains.

IC Role / Device Role / Timing Role: Configured as NOR gate to combine CC1/CC2 status signals into single fault indicator.

Use Value: Reduces arbitration latency to <5 ns, meeting USB-C PD 3.0 timing budget for port partner detection.

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC1G97DBVR	Fixed 6-function capability (no INV/NAND); 5-V tolerant inputs; 5.5-V max V_CC	Requires external pull-down on unused inputs; not suitable for sub-1.2-V operation	Select when interfacing legacy 5-V peripherals and higher supply margin is available
74LVC1G57GW,125	Same 7-function set but in larger TSSOP6 package; no OE pin; 1.65–5.5-V range	Lacks 3-state output; unsuitable for shared bus architectures	Choose when board space allows TSSOP6 and bus contention is not a design requirement

Compared with SN74LVC1G97DBVR and 74LVC1G57GW,125, the 74AXP1G58GM125 uniquely combines 7-function configurability, OE control, sub-1.1-V operation, and XSON8 size-making it optimal for miniaturized, multi-voltage, low-power edge nodes where pin count and leakage are critical.

Availability

74AXP1G58GM125 is available at Aetrix Electronics and suitable for wearable health monitors, smart home motion sensors, industrial wireless nodes, and USB-C power negotiation logic requiring stable component supply and long-term lifecycle support.

Supply support for 74AXP1G58GM125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for consumer, industrial, and automotive markets.

The AXP logic family targets ultra-low-power, space-constrained applications demanding flexible functionality in minimal footprint - especially battery-powered edge devices with mixed-voltage interfaces.

FAQ

What logic functions does the 74AXP1G58GM125 support?

The 74AXP1G58GM125 supports seven distinct logic functions: AND, OR, XNOR, XOR, INV, NAND, and NOR. Selection is determined by the binary state of its two configuration inputs A0 and A1. The truth table is fixed per device revision and documented in Nexperia's datasheet revision 2022-09, Table 9.

Can the 74AXP1G58GM125 operate below 1.2 V?

Yes - the device is fully specified from 1.1 V to 3.6 V. At 1.1 V, propagation delay increases to 12.5 ns (typical), and output drive strength reduces to ±8 mA, but all logic states remain valid and monotonic. This enables use in deep-sleep modes of energy-harvesting systems.

Is the OE pin internally pulled up or down?

The OE pin has no internal pull; it must be actively driven. When left floating, the output enters high-impedance state unpredictably due to noise coupling. For default-enabled operation, tie OE to GND via a 10-kΩ resistor; for default-disabled, tie to V_CC.

Does the 74AXP1G58GM125 require external decoupling?

Yes - a 100-nF X7R ceramic capacitor must be placed between V_CC (Pin 7) and GND (Pin 5), with trace length ≤2 mm. Without this, supply bounce exceeds 150 mV during switching, causing metastability in adjacent logic stages per Nexperia Application Note AN11050.

74AXP1G58GM125 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: *

Package/Case:: -

Packaging:: Bulk

Product Status:: Not For New Designs

Logic Type:: -

Number of Circuits:: -

Number of Inputs:: -

Schmitt Trigger Input:: -

Output Type:: -

Current - Output High, Low:: -

Voltage - Supply:: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

74AXP1G58GM125 FAQ

1.How can I place an order for 74AXP1G58GM125 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74AXP1G58GM125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74AXP1G58GM125 reliable?

The price and inventory of 74AXP1G58GM125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AXP1G58GM125 is usually 5 days.

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Once your 74AXP1G58GM125 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74AXP1G58GM125?

For technical support, including 74AXP1G58GM125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AXP1G58GM125 requirements.

6.How does Aetrix verify that 74AXP1G58GM125 is sourced from the original manufacturer or authorized distributors?

All 74AXP1G58GM125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AXP1G58GM125 meets industry standards.

7.What is the process for return or replacement of 74AXP1G58GM125?

All 74AXP1G58GM125 units undergo pre-shipment inspection (PSI). If there is an issue with 74AXP1G58GM125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74AXP1G58GM125 part is unused and in its original packaging.

Return procedure for 74AXP1G58GM125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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