Nexperia USA Inc. 74AXP1T125GNH

Overview

74AXP1T125 from Nexperia is a dual-supply non-inverting 3-state buffer/line driver with independent input (VCCI) and output (VCCO) rails, enabling bidirectional voltage level translation between 0.7 V–2.75 V and 1.2 V–5.5 V domains. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and operates across –40 °C to +85 °C. Used in mixed-voltage I/O interfacing between low-power microcontrollers and higher-voltage peripherals.

For engineers reviewing the 74AXP1T125 datasheet, 74AXP1T125 pinout, 74AXP1T125 application, or 74AXP1T125 equivalent, key selection criteria include dual-rail supply flexibility, sub-1 ns transition time at 5 V, IOFF leakage < 0.5 μA at 85 °C, and XSON6 package compatibility with high-density PCB layouts.

Technical Context

The device implements a single-channel non-inverting logic gate with separate VCCI (input reference) and VCCO (output reference) supplies, allowing asymmetric voltage translation-e.g., 1.2 V MCU GPIO to 3.3 V sensor interface. OE control enables high-impedance output state independent of supply states.

Schmitt-trigger inputs tolerate slow edges (Δt/ΔV ≤ 200 ns/V), while IOFF circuitry actively disables outputs during power-down, blocking backflow current when either supply is off. Static ICCI/ICCO remain below 0.5 μA and 1.8 μA respectively at 85 °C.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT1115); no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm; thermal pad not present; pin 1 indicator located lower-left of marking code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-supply buffer applications.

Compared with SN74AVC1T45DBVR and TXB0101DCKR, the 74AXP1T125 uniquely combines Schmitt-trigger inputs, true IOFF, and sub-2 ns enable timing in a 0.9 × 1.0 mm XSON6 footprint-making it optimal for space-constrained, mixed-voltage control signaling where reliability under partial power-down is mandatory.

Availability

74AXP1T125 is available at Aetrix Electronics and suitable for industrial sensor interface, low-power MCU I/O expansion, and automotive body control modules requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for 74AXP1T125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable components for automotive, industrial, mobile, and computing markets, with leadership in logic, discretes, and MOSFETs.

The 74AXP series targets ultra-low-power, mixed-voltage interface applications-designed specifically for energy-efficient systems requiring robust level translation, minimal leakage, and compact packaging.

FAQ

What is the maximum allowable voltage difference between VCCI and VCCO?

The datasheet does not specify a maximum differential voltage limit. Absolute maximum ratings define VCCI ≤ 3.3 V and VCCO ≤ 6.0 V independently, with no restriction on their relative values. Operation is valid for any combination within those bounds-e.g., VCCI = 0.7 V and VCCO = 5.5 V is fully supported and commonly used in 1.2 V-to-5 V translation.

Does the 74AXP1T125 support hot insertion when one supply is powered and the other is off?

Yes-its IOFF circuitry actively disables the output stage when either VCCI or VCCO is at 0 V, limiting OFF-state leakage to ±0.5 μA max at 85 °C. This prevents back-current damage during live insertion into partially powered systems, satisfying hot-swap requirements per JEDEC JESD78D Class II latch-up immunity.

Can the OE pin be driven from a different voltage domain than VCCI?

No-OE is referenced solely to VCCI and must be driven between 0 V and VCCI. Driving OE from a higher voltage (e.g., 3.3 V while VCCI = 1.2 V) violates the VI absolute maximum rating (–0.5 V to 3.3 V) and risks latch-up or permanent damage. OE must be controlled by logic within the VCCI domain.

Is there a recommended PCB layout practice for minimizing noise coupling between VCCI and VCCO?

Yes-separate VCCI and VCCO power planes should be routed with dedicated decoupling: 100 nF X7R ceramic capacitors placed ≤2 mm from each supply pin, with short, wide traces to local ground. Avoid shared vias or copper pours between domains; use split ground plane with single-point connection near GND pin to prevent ground loops.