Nexperia USA Inc. 74AXP1T14GXH

Overview

74AXP1T14GX from Nexperia is a dual-supply Schmitt trigger inverter IC with independent input (VCCI) and output (VCCO) supply rails, enabling bidirectional voltage level translation between 0.7 V–2.75 V and 1.2 V–5.5 V domains. It features one logic input (A), one inverted output (Y), IOFF partial power-down protection, and operates across –40 °C to +85 °C. Used in low-power I/O bridging for mixed-voltage microcontroller interfaces and sensor signal conditioning.

For engineers reviewing the 74AXP1T14GX datasheet, 74AXP1T14GX pinout, 74AXP1T14GX application, or 74AXP1T14GX equivalent, this page delivers verified electrical parameters, package-specific pin mapping, real-world use cases, and validated alternative parts - all grounded in Nexperia's Rev. 3 product data sheet dated 2 February 2022.

Technical Context

This device implements a single-channel Schmitt-trigger inverter with hysteresis (VH = 0.2–1.0 V) referenced to VCCI, ensuring noise immunity in noisy digital environments. Its dual-rail architecture isolates input and output domains, allowing VCCI and VCCO to operate at different voltages without internal level-shifting circuitry.

The IOFF circuit actively disables the output when either supply is powered down, blocking backflow current (≤±0.5 μA at 85 °C) and meeting JEDEC JESD78D Class II latch-up requirements (>100 mA). Input leakage remains ≤±0.5 μA over full temperature range, supporting reliable partial-power-down operation in battery-backed systems.

Key Specifications

Pinout & Package

X2SON5 (SOT1226-3) package: plastic thermal-enhanced extremely thin small outline, 5-terminal, no leads, body size 0.8 × 0.8 × 0.32 mm, pin 1 indicator located on lower-left corner below marking code "rL".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-supply Schmitt trigger inverter applications.

Compared with 74LVC1G14GV and SN74AXP1T14DCKR, the 74AXP1T14GX uniquely enables true bidirectional voltage translation in a 0.64 mm² footprint while delivering lowest input capacitance (0.6 pF) and best partial-power-down isolation (≤±0.5 μA), making it optimal for space-constrained, multi-rail portable electronics.

Availability

74AXP1T14GX is available at Aetrix Electronics and suitable for industrial sensor interface, microcontroller I/O bridging, USB-C power delivery sequencing, and low-power wearable subsystems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74AXP1T14GX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.

The 74AXP series targets ultra-low-power, dual-supply logic translation for battery-operated and mixed-voltage embedded systems - designed specifically to replace discrete level-shifters while minimizing board area and leakage.

FAQ

Can 74AXP1T14GX operate with VCCI = 0 V while VCCO = 3.3 V?

Yes - the device enters IOFF state when VCCI = 0 V, disabling the output (Y) to high-impedance and limiting leakage to ≤±0.5 μA. This prevents back-current into the unpowered input domain and satisfies JEDEC JESD78D Class II latch-up immunity requirements.

What is the minimum VCCI required to guarantee valid logic thresholds?

The minimum functional VCCI is 0.7 V per datasheet Table 6. Below this, VT+ and VT− become undefined and hysteresis collapses. At VCCI = 0.75 V, VT+ = 0.23 V and VT− = 0.15 V (typical), yielding 80 mV usable hysteresis - sufficient for low-noise, well-regulated 0.8 V domains.

Does the 74AXP1T14GX support hot-swap insertion into a live VCCO rail?

Yes - the IOFF circuit activates when VCCI is unpowered or near 0 V, forcing Y into high-Z with ≤±0.5 μA leakage. Combined with ESD ratings (HBM >2000 V, CDM >1000 V), this enables safe insertion into powered-backplane systems without risk of bus contention or latch-up.

How does propagation delay vary with load capacitance?

tpd increases linearly with CL: e.g., at VCCI = 2.5 V and VCCO = 5.0 V, tpd rises from 5.1 ns (CL = 0 pF) to 11.5 ns (CL = 30 pF) per Figure 8. The device's low CO = 1.8 pF minimizes this slope, making it suitable for driving moderate fanout without added buffering.