Nexperia USA Inc. 74AXP1T34GMH

Overview

74AXP1T34GMH from Nexperia is a dual-supply translating buffer IC with independent input (VCCI) and output (VCCO) rails, enabling bidirectional voltage level translation between 0.7 V–2.75 V and 1.2 V–5.5 V domains. It features Schmitt-trigger inputs for noise immunity, IOFF circuitry for partial power-down protection, and operates across –40 °C to +85 °C. Used in mixed-voltage I/O interfacing between low-power microcontrollers and higher-voltage peripherals.

For engineers reviewing the 74AXP1T34GMH datasheet, 74AXP1T34GMH pinout, 74AXP1T34GMH application, or 74AXP1T34GMH equivalent, key selection criteria include verified dual-rail supply ranges, IOFF-enabled power sequencing, input/output capacitance values (CI = 0.6 pF, CO = 1.8 pF), propagation delay under load (e.g., 2.2 ns min at VCCI = 2.5 V / VCCO = 3.3 V), and JEDEC-compliant interface standards including JESD8-12A.01 and JESD8-C.

Technical Context

This device implements a single-channel unidirectional buffer with separate VCCI and VCCO supplies, where input logic thresholds scale with VCCI and output swing references VCCO. The Schmitt-trigger input ensures robust operation with slow-rising signals, while IOFF disables the output when either supply is near 0 V to prevent backflow current.

It supports JEDEC-compliant voltage interfaces across five standard families (JESD8-12A.01 through JESD12-6), enabling interoperability with 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V logic systems. Static current remains below 0.5 μA (ICCI) and 1.8 μA (ICCO) at 85 °C, and dynamic power dissipation is characterized by CPD = 0.4 pF (VCCI) and 7.1 pF (VCCO) at typical operating points.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm (SOT886). Pin 1 index located on lower-left corner beneath marking code "rQ".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-supply translating buffer applications.

Compared with TXS0101DCUR and SN74AVCH1T45DBVR, the 74AXP1T34GMH uniquely supports 5 V output domains, integrates Schmitt-trigger noise rejection, and delivers lowest input capacitance (0.6 pF) - making it optimal for high-speed, mixed-voltage, and noise-sensitive embedded interfaces.

Availability

74AXP1T34GMH is available at Aetrix Electronics and suitable for industrial sensor interface, automotive body control, USB-C power delivery sequencing, and low-power MCU I/O expansion requiring stable component supply across extended temperature and mixed-voltage conditions.

Supply support for 74AXP1T34GMH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer applications.

The 74AXP1T34 belongs to Nexperia's AXP ultra-low-power logic family, engineered specifically for voltage translation in space-constrained, battery-sensitive, and thermally demanding embedded systems.

FAQ

Can 74AXP1T34GMH translate from 5 V to lower voltages?

No - the 74AXP1T34GMH is unidirectional: input (A) is referenced to VCCI and must not exceed 2.75 V, while output (Y) swings between 0 V and VCCO (up to 5.5 V). It translates low-voltage inputs to higher-voltage outputs only. For 5 V-to-low-voltage translation, a dedicated bidirectional or reverse-configured device is required.

What happens to the output when VCCI = 0 V but VCCO = 3.3 V?

When VCCI = 0 V, the IOFF circuit activates, forcing the Y output into high-impedance (Z) state regardless of VCCO voltage or input signal. This prevents back-current from VCCO into the disabled input stage, protecting upstream circuitry during power sequencing or fault conditions.

Is pin 5 (n.c.) required to be left floating?

Yes - pin 5 is internally unconnected and must remain electrically floating. Connecting it to GND, VCCI, or VCCO violates the SOT886 package specification and may cause unpredictable behavior or increased leakage due to parasitic coupling in the XSON6 die layout.

Does the Schmitt-trigger input affect propagation delay variation?

Yes - the Schmitt-trigger action increases input hysteresis but does not degrade propagation delay. Measured tpd remains consistent across input transition rates up to 200 ns/V, and the device guarantees monotonic delay behavior even with slow-rising signals, unlike standard CMOS buffers which may oscillate or exhibit metastability.