Nexperia USA Inc. 74AXP1T57GNX
- Part No.:
- 74AXP1T57GNX
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN
- Datasheet:
-
74AXP1T57GNX.pdf
- Description:
- DUAL SUPPLY GATE SOT1116
- Quantity:
- Payment:

- Shipping:

Inventory:4,200
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Product details
Overview
74AXP1T57 from Nexperia is a dual-supply configurable logic gate with Schmitt-trigger inputs, three inputs (A/B/C), one output (Y), and independent input/output supply rails (VCCI: 0.7–2.75 V; VCCO: 1.2–5.5 V). It supports seven logic functions (AND, OR, NAND, NOR, XNOR, inverter, buffer) via pin-strapping and enables bidirectional voltage level translation between disparate logic domains. Used in mixed-voltage I/O interfacing on industrial microcontroller peripherals.
For engineers reviewing the 74AXP1T57 datasheet, 74AXP1T57 pinout, 74AXP1T57 application, or 74AXP1T57 equivalent, this page delivers verified functional configuration options, IOFF-enabled partial power-down behavior, Schmitt-trigger noise immunity specs, and package-specific thermal derating data for SOT1116 (XSON8).
Technical Context
The device implements a single configurable gate using pass-transistor logic controlled by static input combinations, where A/B/C determine function selection per Table 5. Its dual-supply architecture isolates input threshold referencing (to VCCI) from output swing (referenced to VCCO), enabling true level-shifting without external biasing.
Schmitt-trigger inputs provide hysteresis (VH = 0.2–1.0 V) across VCCI ranges, ensuring robust noise rejection in noisy environments. The IOFF circuit disables Y when either supply is at 0 V, blocking backflow current and supporting hot-swap and power-gating use cases in battery-backed systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCCI range | 0.7 V to 2.75 V: sets input logic thresholds and determines Schmitt-trigger hysteresis voltage |
| VCCO range | 1.2 V to 5.5 V: defines output HIGH/LOW voltage levels and drives load capacitance up to 5 pF |
| Propagation delay (tpd) | 7.2–225 ns: varies with VCCI/VCCO combination and temperature; min 7.2 ns at VCCI=2.7 V, VCCO=5.0 V, Tamb=25 °C |
| Input capacitance (CI) | 0.6 pF typical: minimizes loading on upstream drivers and preserves signal integrity at high frequencies |
| IOFF leakage | ±2.0 μA max at 125 °C: ensures safe isolation during partial power-down without requiring external pull resistors |
| ESD rating | HBM >2 kV, CDM >1 kV: meets industrial IEC 61000-4-2 system-level ESD immunity requirements |
| Operating temperature | −40 °C to +125 °C: qualified for under-hood automotive and industrial control applications |
Pinout & Package
XSON8 package (SOT1116): extremely thin small outline, no leads, 8-terminal, body size 1.2 × 1.0 × 0.35 mm, thermal pad not present, pin 1 marked by lower-left corner dot below marking code "rD".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCCI | Input supply rail | Reference for all input thresholds and Schmitt-trigger hysteresis; must be stable before enabling inputs |
| A, B, C | Configurable logic inputs | Static strapping pins that select logic function per Table 5; tolerate up to 2.75 V regardless of VCCI |
| GND (pins 4,5) | Digital ground | Common return for both supplies; both pins must be connected to 0 V for proper IOFF operation |
| Y | Configurable logic output | Active-drive output referenced to VCCO; enters high-Z state when VCCI = 0 V or VCCO = 0 V due to IOFF |
| VCCO | Output supply rail | Sets VOH/VOL levels and powers output stage; independent of VCCI to enable level translation |
Key Features
| Feature | Design Value |
|---|---|
| Dual-supply level translation | VCCI and VCCO operate independently, allowing interface between 1.2 V MCU I/O and 3.3 V sensor bus without external translators |
| Schmitt-trigger inputs | VT+ and VT− thresholds scale with VCCI (e.g., 0.4VCCI/0.3VCCI at 1.2 V), rejecting <10% VCCO noise on inputs |
| IOFF partial power-down | Automatically disables Y and limits ICCO/ICCI to ≤2.0 μA when either supply drops to 0 V, preventing backfeed in modular systems |
| Ultra-low dynamic power | CPD = 0.6 pF at VCCI = 1.2 V enables sub-μW switching power at 1 MHz with 3 toggling inputs |
| JEDEC-compliant voltage standards | Meets JESD8-12A.01 through JESD12-6 across full VCCI/VCCO range, ensuring interoperability with JEDEC-specified logic families |
Applications
| Industrial PLC I/O Expansion | Automotive Body Control Module |
|---|---|
Use Scenario: Interfacing 1.8 V microcontroller GPIOs to legacy 5 V discrete sensors and actuators in programmable logic controllers. IC Role / Device Role / Timing Role: Configured as a level-translating buffer to drive 5 V loads while accepting 1.8 V inputs; Schmitt-trigger rejects EMI from relay coils. Use Value: Eliminates need for discrete MOSFET translators and reduces board space by 60% versus dual-buffer solutions. | Use Scenario: Signal conditioning for LIN bus wake-up detection in door module ECUs where 12 V supply is unstable during ignition cycles. IC Role / Device Role / Timing Role: Configured as an inverter with VCCI = 1.2 V (from always-on LDO) and VCCO = 5 V (from switched supply); IOFF blocks backfeed when main supply drops. Use Value: Enables reliable wake-up detection during brown-out conditions without external diode protection or leakage mitigation. |
| Medical Wearable Sensor Hub | IoT Edge Node Power Management |
Use Scenario: Aggregating outputs from multiple low-power analog front-ends (0.9 V ADCs) into a 3.3 V MCU host in compact wearable devices. IC Role / Device Role / Timing Role: Configured as NAND gate to combine sensor alert signals; Schmitt inputs reject RF coupling from Bluetooth antenna. Use Value: Reduces active current to <1 μA at 85 °C, extending battery life beyond 12 months in sleep mode. | Use Scenario: Controlling power sequencing of 1.1 V FPGA core, 1.8 V I/O bank, and 3.3 V communication PHY in battery-powered edge nodes. IC Role / Device Role / Timing Role: Configured as OR gate to generate global reset from individual rail monitors; VCCI tied to 1.1 V rail, VCCO to 3.3 V rail. Use Value: Ensures deterministic reset assertion even if 1.1 V rail collapses first, preventing FPGA configuration corruption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G97DRYR | Single-supply only (1.65–5.5 V); no VCCI/VCCO separation; lacks IOFF and Schmitt inputs | Cannot perform level translation; unsuitable for partial power-down systems | Select only when interfacing same-voltage domains and lowest cost is primary constraint |
| 74LVC1G98GW,125 | Single-supply (1.65–5.5 V); includes Schmitt inputs but no IOFF; higher CPD (12 pF) | Accepts noisy inputs but cannot isolate powered-down sections; higher dynamic power | Prefer when noise immunity is critical but power gating is not required |
Compared with SN74LVC1G97DRYR and 74LVC1G98GW,125, the 74AXP1T57 uniquely supports dual-rail level translation and IOFF-based power domain isolation-critical for mixed-voltage, energy-constrained systems where supply sequencing and EMI resilience are design priorities.
Availability
74AXP1T57 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, medical wearable sensor hubs, and IoT edge node power management requiring stable component supply across extended temperature ranges.
Supply support for 74AXP1T57 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer headquartered in Nijmegen, Netherlands, specializing in high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.
The AXP logic family targets ultra-low-power, mixed-voltage digital interfacing, with the 74AXP1T57 specifically engineered for space-constrained applications needing configurable logic plus robust level translation and power-domain isolation.
FAQ
Can 74AXP1T57 be used with VCCI = 0 V while VCCO remains active?
No. When VCCI = 0 V, the internal input circuitry is disabled and the output enters high-impedance (Z) state regardless of VCCO voltage or input states. This is part of the IOFF specification to prevent back-current flow-VCCI must be ≥0.7 V for functional operation.
What is the maximum capacitive load the Y output can drive reliably?
The Y output is characterized up to 5 pF load capacitance per Figure 16–21. Driving >5 pF may increase propagation delay beyond datasheet limits (e.g., tpd rises from 7.2 ns to >18 ns at CL = 30 pF with VCCO = 5.0 V), potentially violating timing budgets in high-speed interfaces.
How does the Schmitt-trigger hysteresis change with VCCI?
Hysteresis voltage (VH) scales linearly with VCCI: 0.06VCCI–0.5VCCI at 0.75–0.85 V, 0.1VCCI–0.4VCCI at 1.1–1.95 V, and 0.2VCCI–1.0VCCI at 2.3–2.7 V. At VCCI = 1.2 V, VH is 0.12–0.48 V, providing ≥100 mV noise margin against fast transients.
Is the 74AXP1T57 compliant with AEC-Q200 for automotive use?
No. While qualified from −40 °C to +125 °C and meeting JEDEC standards, the 74AXP1T57 is not AEC-Q200 stress-tested. For automotive applications requiring AEC-Q200 qualification, Nexperia's automotive-grade 74AUP1T57 variant (SOT363 package) is recommended instead.
74AXP1T57GNX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AXP
- Package/Case:
- 8-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Configurable Multiple Function
- Number of Circuits:
- 1
- Number of Inputs:
- 3
- Schmitt Trigger Input:
- Yes
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 12mA, 12mA
- Voltage - Supply:
- 0.7V ~ 2.75V, 1.2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (1.2x1)
74AXP1T57GNX FAQ
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6.How does Aetrix verify that 74AXP1T57GNX is sourced from the original manufacturer or authorized distributors?
All 74AXP1T57GNX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AXP1T57GNX meets industry standards.
7.What is the process for return or replacement of 74AXP1T57GNX?
All 74AXP1T57GNX units undergo pre-shipment inspection (PSI). If there is an issue with 74AXP1T57GNX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AXP1T57GNX part is unused and in its original packaging.
Return procedure for 74AXP1T57GNX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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