Nexperia USA Inc. 74AXP2G07GN125

Overview

74AXP2G07GN125 from Nexperia is a dual non-inverting buffer IC with open-drain outputs, Schmitt-trigger inputs, and IOFF partial power-down capability. It operates across 0.7 V–2.75 V supply, delivers <0.6 μA static ICC at 85 °C, and features 0.5 pF input capacitance and 0.7 pF output capacitance. Used in low-voltage I²C bus level-shifting and mixed-voltage interface translation.

For engineers reviewing the 74AXP2G07GN125 datasheet, 74AXP2G07GN125 pinout, 74AXP2G07GN125 application, or 74AXP2G07GN125 equivalent, key selection criteria include open-drain drive strength (±20 mA), IOFF-enabled backflow prevention during power sequencing, Schmitt-trigger noise immunity, and XSON6 (SOT1115) package compatibility with high-density PCB layouts.

Technical Context

This device integrates two independent non-inverting buffers, each with Schmitt-trigger inputs enabling robust operation under slow-rising/falling signals and high noise environments. The IOFF circuit actively disables outputs when VCC = 0 V, blocking destructive back-current flow between powered and unpowered domains.

It supports multi-voltage domain interfacing via wide VCC range (0.7 V–2.75 V) and input tolerance up to 2.75 V regardless of supply level. Propagation delay ranges from 1.2 ns (VCC = 2.7 V) to 31 ns (VCC = 0.75 V), with transition time ≤0.9 ns at 2.7 V, making it suitable for sub-100 MHz digital signal conditioning.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal, body size 0.9 × 1.0 × 0.35 mm, thermal padless, pin 1 marked by lower-left corner indicator below marking code "r7".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual open-drain buffer applications.

Compared with 74LVC2G07GM and SN74LVC2G07DCKR, the 74AXP2G07GN125 uniquely supports sub-1 V operation, integrates Schmitt-trigger inputs for noise resilience, and provides IOFF protection-making it the sole option for energy-harvesting and advanced low-power embedded systems requiring safe multi-rail sequencing.

Availability

74AXP2G07GN125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C level-shifting, wearable controller wake-up circuits, and hot-swappable module interfaces requiring stable component supply across extended temperature and low-voltage operating conditions.

Supply support for 74AXP2G07GN125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and discrete components, headquartered in Nijmegen, Netherlands.

The 74AXP series targets ultra-low-power portable and battery-operated applications, delivering optimized performance at supply voltages down to 0.7 V while maintaining robustness in industrial environments.

FAQ

Can 74AXP2G07GN125 drive a 10 kΩ pull-up resistor at 2.7 V while meeting I²C timing?

Yes. With VOL ≤0.7 V at IO = 8 mA and typical output capacitance of 0.7 pF, the buffer achieves rise times compatible with standard-mode (100 kHz) and fast-mode (400 kHz) I²C. At 2.7 V and 10 kΩ pull-up, calculated rise time is ~19 ns - well within I²C specification limits.

Does the IOFF feature activate automatically when VCC drops below a threshold?

Yes. IOFF engages when VCC falls to 0 V (or near 0 V), disabling both outputs and limiting back-current to ±0.5 μA maximum. No external control signal is required - the function is intrinsic to the silicon design and activates during power ramp-down or complete loss of supply.

Is pin 1 orientation consistent across all XSON6 variants (SOT886, SOT1115, SOT1202)?

Yes. All XSON6 packages - including SOT1115 (74AXP2G07GN) - locate pin 1 at the lower-left corner beneath the marking code "r7", verified in Figures 4 and 14 of the datasheet. This ensures mechanical and layout compatibility across package options.

What is the maximum capacitive load the outputs can drive while maintaining 1.2 ns propagation delay?

At VCC = 2.7 V, the 1.2 ns minimum propagation delay is specified with CL = 5 pF (per Table 10). Driving >10 pF increases tpd nonlinearly - Figure 7 shows tPZL rises to ~4 ns at CL = 40 pF. For sub-2 ns timing, keep total load ≤7 pF including trace and probe capacitance.