Nexperia USA Inc. 74AXP2G17GNH

Overview

74AXP2G17GNH from Nexperia is a dual Schmitt trigger buffer IC designed for signal conditioning in ultra-low-voltage digital systems. It operates across 0.7 V to 2.75 V supply, delivers jitter-free output with hysteresis (VH = 0.1–1.0 V), achieves propagation delay as low as 1.1 ns at 2.3–2.7 V, and features IOFF circuitry enabling safe partial power-down. It is used in battery-powered sensor interfaces and I²C bus level-shifting circuits where noise immunity and sub-1 µA static current are critical.

For engineers reviewing the 74AXP2G17GNH datasheet, 74AXP2G17GNH pinout, 74AXP2G17GNH application, or 74AXP2G17GNH equivalent, this page provides verified functional role, validated XSON6 (SOT1115) package mapping, confirmed Schmitt threshold behavior (VT+ = 0.4–0.9 VCC), real-world dynamic power data (CPD = 2.5 pF @ 1.2 V), and precise IOFF leakage specs (≤0.5 µA @ 85 °C).

Technical Context

This device implements two independent Schmitt-trigger input buffers with rail-to-rail output swing and symmetric hysteresis-enabling clean signal regeneration from slow-rising or noisy inputs. Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±20 mA while maintaining input tolerance to 2.75 V regardless of supply state.

The architecture supports mixed-voltage domain interfacing: inputs accept 0–2.75 V even during power-down, and output drive strength scales with VCC (VOH ≥ 0.825 V @ 1.1 V/−2 mA; VOL ≤ 0.275 V @ 1.1 V/2 mA). Threshold voltages (VT+, VT−) are dynamically scaled to VCC, ensuring consistent noise margin across the full 0.7–2.75 V operating range.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin no-lead outline, 0.9 × 1.0 × 0.35 mm body, wettable flank terminals for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual Schmitt trigger buffer applications.

Compared with 74LVC2G17GW and SN74LVC2G17DCKR, the 74AXP2G17GNH uniquely supports sub-1 V operation, delivers 15× lower static current, and provides hardware-enforced IOFF isolation-making it the sole option for energy-constrained, multi-voltage, or hot-swap-sensitive applications.

Availability

74AXP2G17GNH is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable device power sequencing, I²C bus level translation, and low-power MCU reset conditioning requiring stable component supply across extended temperature ranges (−40 °C to +85 °C).

Supply support for 74AXP2G17GNH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies-delivering high-performance, reliable, and scalable components for automotive, industrial, and consumer markets.

The AXP logic family targets ultra-low-power portable and battery-operated applications, emphasizing sub-1 V operation, nanowatt static consumption, and robust IOFF behavior for modern multi-rail system architectures.

FAQ

Can 74AXP2G17GNH operate reliably at 0.7 V supply?

Yes. The device is fully characterized from 0.7 V to 2.75 V per JEDEC standards JESD8-12A.01 through JESD8-5A.01. At 0.7 V, propagation delay remains within specification (tpd ≤ 136 ns), VOH reaches 0.69 V, and ICC stays below 0.6 µA-enabling direct use with 0.8 V-core processors and energy-harvesting power supplies.

What happens to the outputs when VCC is disconnected?

When VCC = 0 V, the IOFF circuit forces both 1Y and 2Y outputs into high-impedance state. Measured IOFF leakage is ≤±0.5 µA at 85 °C, preventing damaging backflow current into powered downstream circuits-even if inputs or outputs are biased to 2.75 V during power-down.

Does the 74AXP2G17GNH require external pull-up resistors?

No. As a true CMOS buffer with push-pull outputs, it drives HIGH and LOW actively without external resistors. Pull-ups are unnecessary unless interfacing with open-drain buses (e.g., I²C), where external pull-ups remain required per bus specification-not device limitation.

How does its hysteresis improve noise immunity compared to standard buffers?

Its programmable hysteresis (VH = 0.1–1.0 V) creates distinct VT+ and VT− thresholds-requiring noise spikes to exceed ΔV = VH to falsely trigger. This rejects sub-threshold interference that would cause chatter in non-Schmitt buffers, especially critical on long traces or near switching regulators.