Nexperia USA Inc. 74AXP2G17GSH
- Part No.:
- 74AXP2G17GSH
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AXP2G17GSH.pdf
- Description:
- IC BUFFER NON-INVERT 2.75V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:5,000
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Product details
Overview
74AXP2G17GSH from Nexperia is a dual Schmitt trigger buffer IC designed for signal conditioning in ultra-low-voltage digital systems. It provides hysteresis-based noise immunity, operates across 0.7 V to 2.75 V supply, delivers sub-3 ns propagation delay at 2.3–2.7 V, and features IOFF partial power-down protection. It is used in I²C bus level-shifting interfaces and battery-powered sensor signal cleanup circuits.
For engineers reviewing the 74AXP2G17GSH datasheet, 74AXP2G17GSH pinout, 74AXP2G17GSH application, or 74AXP2G17GSH equivalent, this page delivers verified electrical parameters, XSON6 package mapping, Schmitt threshold behavior, IOFF leakage specs, and real-world use cases in low-power mixed-signal designs.
Technical Context
This device implements two independent Schmitt-trigger input buffers with rail-to-rail input tolerance up to 2.75 V and output drive capability of ±8 mA at 2.3 V. Its hysteresis voltage (VH) scales with VCC-ranging from 0.2 V to 1.0 V-and supports clean edge regeneration for slow-rising signals like RC-debounced switches or analog sensor outputs.
The IOFF circuit ensures bidirectional isolation during partial power-down: when VCC = 0 V, input/output terminals are high-impedance with ≤0.5 µA leakage, preventing backflow current into powered subsystems. Static ICC remains ≤0.6 µA at +85 °C, enabling always-on monitoring nodes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 0.7 V to 2.75 V - enables direct interface with 0.8 V logic, 1.2 V cores, and 1.8/2.5 V peripherals without level shifters. |
| Propagation delay (tpd) | 1.1 ns (min) to 3.3 ns (max) at 2.3–2.7 V - supports >300 MHz signal edge rates in timing-critical paths. |
| Hysteresis voltage (VH) | 0.2 V to 1.0 V depending on VCC - rejects noise spikes up to 10% of VCC while preserving signal integrity. |
| IOFF leakage current | ≤0.5 µA at VCC = 0 V - prevents cross-talk and power loss when one domain is powered down in multi-rail systems. |
| Input capacitance (CI) | 0.5 pF typical - minimizes loading on high-impedance sources such as crystal oscillator outputs or MEMS sensor nodes. |
| Operating temperature | −40 °C to +85 °C - qualified for industrial-grade embedded control and portable electronics environments. |
Pinout & Package
The 74AXP2G17GSH is housed in an XSON6 package (SOT1202), measuring 1.0 mm × 1.0 mm × 0.35 mm, with no leads and wettable flanks for automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A | Channel 1 input | Accepts input voltages up to 2.75 V regardless of VCC; triggers on VT+ and VT− thresholds. |
| GND | Ground reference | 0 V return path for both supply and signal; must be low-inductance for stable Schmitt operation. |
| 2A | Channel 2 input | Independent Schmitt input with identical hysteresis behavior and voltage tolerance as Pin 1A. |
| 2Y | Channel 2 output | CMOS-compatible push-pull output; drives loads up to ±8 mA while maintaining VOL ≤ 0.7 V at 2.3 V. |
| VCC | Power supply | Single-supply rail powering both channels; IOFF activates automatically when VCC = 0 V. |
| 1Y | Channel 1 output | Matched output drive strength and transition time (tt ≤ 1.0 ns at 2.7 V) to 2Y for balanced timing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent Schmitt inputs | Enables simultaneous cleanup of two asynchronous signals (e.g., reset and interrupt lines) without shared timing skew. |
| IOFF partial power-down | Eliminates backflow current during VCC ramp-down, allowing safe hot-insertion in modular power domains. |
| Sub-1 pF total capacitance | Reduces signal reflection and ringing on high-speed traces; critical for maintaining integrity on <10 mm PCB runs. |
| JESD8-compliant voltage ranges | Guarantees interoperability with JEDEC-standard 1.2 V, 1.5 V, 1.8 V, and 2.5 V logic families without external biasing. |
| HBM ESD rating >2 kV | Withstands handling and board-level transients without additional protection components in consumer-grade assemblies. |
Applications
| Industrial Sensor Interface | I²C Bus Level Translation |
|---|---|
Use Scenario: Cleaning noisy analog switch or thermistor output before ADC sampling in a programmable logic controller. IC Role / Device Role / Timing Role: Schmitt buffer converts slow RC-filtered edges into monotonic, jitter-free digital transitions synchronized to system clock domain. Use Value: Eliminates false triggering caused by EMI-induced oscillation on long sensor cables, reducing firmware debounce overhead by >90%. |
Use Scenario: Bridging 1.2 V microcontroller I²C pins to 1.8 V EEPROM in a wearables power-management subsystem. IC Role / Device Role / Timing Role: Dual buffer isolates voltage domains while preserving SCL/SDA edge rates and meeting I²C rise-time requirements (<1000 ns). Use Value: Enables direct interconnection without external MOSFET translators, saving 2.5 mm² PCB area and eliminating gate-charge delay uncertainty. |
| Battery-Powered Reset Circuit | Low-Power Keypad Debounce |
Use Scenario: Generating clean POR (power-on reset) signal from a slow-rising LDO output in a Bluetooth LE module. IC Role / Device Role / Timing Role: First-stage Schmitt input sharpens LDO ramp; second stage provides glitch-free reset assertion to MCU core. Use Value: Ensures deterministic reset release at precisely defined VCC threshold (e.g., 0.9 V), avoiding brown-out lockup during cold-start. |
Use Scenario: Debouncing mechanical keypad matrix rows/columns in a medical handheld device operating from coin-cell battery. IC Role / Device Role / Timing Role: Converts bounce-prone mechanical contact closures into single, clean logic pulses for GPIO interrupt detection. Use Value: Reduces average current draw to <1 µA during standby by eliminating continuous polling, extending battery life by 3× versus RC+MCU solution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual Schmitt trigger applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G17DBVR | Wider VCC range (1.65–5.5 V); higher ICC (10 µA typ); no IOFF; 5-pin SOT-23 package. | Requires external pull-ups for open-drain I²C; unsuitable for sub-1.2 V domains or partial power-down. | Select only if interfacing legacy 3.3 V peripherals and board space permits larger footprint. |
| 74LVC2G17GW,125 | Same XSON6 package; identical pinout; but lacks IOFF and has higher CPD (6.5 pF vs 2.5 pF at 1.2 V). | Cannot safely isolate during power sequencing; higher dynamic power limits use in always-on sensor nodes. | Use only in fixed-rail, full-power systems where IOFF is not required and 2.5× higher switching loss is acceptable. |
Compared with SN74LVC2G17DBVR and 74LVC2G17GW,125, the 74AXP2G17GSH uniquely combines sub-1 V operation, IOFF isolation, and <0.6 µA static current-making it the sole choice for energy-harvesting and multi-rail IoT endpoints requiring guaranteed signal integrity during power transitions.
Availability
74AXP2G17GSH is available at Aetrix Electronics and suitable for industrial sensor interfaces, battery-powered reset generation, I²C level translation, and low-power keypad debounce requiring stable component supply across extended temperature and voltage ranges.
Supply support for 74AXP2G17GSH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and mobile markets.
The AXP ultra-low-power logic family targets energy-constrained applications-designed specifically for sub-1 V operation, minimal dynamic/static power, and robust partial-power-down behavior in modern mixed-signal SoC subsystems.
FAQ
What is the minimum supply voltage at which 74AXP2G17GSH guarantees full functionality?
The device is fully specified from 0.7 V to 2.75 V per JEDEC standards JESD8-12A.01 through JESD8-5A.01. At 0.7 V, propagation delay increases to 39 ns max and hysteresis narrows to 0.06×VCC, but all logic functions remain operational with VIH/VIL margins preserved. No derating or external biasing is required.
Can 74AXP2G17GSH be used to interface 3.3 V signals to a 1.2 V powered system?
No-inputs tolerate up to 2.75 V absolute maximum, and VCC must be ≥VI to avoid forward-biasing internal clamps. For 3.3 V to 1.2 V translation, use a dedicated level shifter like NXSA1T45. The 74AXP2G17GSH supports only down-translation within its own VCC range (e.g., 2.5 V input to 1.2 V VCC is valid).
How does the IOFF feature behave when VCC is ramping from 0 V to nominal?
IOFF activates when VCC drops below ~0.2 V and remains active until VCC exceeds ~0.4 V. During this window, both inputs and outputs present >100 MΩ impedance with ≤0.5 µA leakage-preventing current flow between powered and unpowered sections. This behavior is tested per JESD78 Class II latch-up conditions.
Is the 74AXP2G17GSH pin-compatible with other XSON6 dual Schmitt buffers?
Yes-it shares identical SOT1202 pinout (1A-GND-2A-2Y-VCC-1Y) with 74LVC2G17GW,125 and 74AUP2G17GS. However, electrical differences exist: AXP offers lower ICC and IOFF, while AUP provides better noise margin at 1.2 V and LVC supports higher VCC. Mechanical drop-in replacement is possible; functional validation is required.
74AXP2G17GSH Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AXP
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Not For New Designs
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- Schmitt Trigger
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 0.7V ~ 2.75V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON, SOT1202 (1x1)
74AXP2G17GSH FAQ
1.How can I place an order for 74AXP2G17GSH through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AXP2G17GSH on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AXP2G17GSH reliable?
The price and inventory of 74AXP2G17GSH are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AXP2G17GSH is usually 5 days.
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Once your 74AXP2G17GSH order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AXP2G17GSH?
For technical support, including 74AXP2G17GSH datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AXP2G17GSH requirements.
6.How does Aetrix verify that 74AXP2G17GSH is sourced from the original manufacturer or authorized distributors?
All 74AXP2G17GSH products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AXP2G17GSH meets industry standards.
7.What is the process for return or replacement of 74AXP2G17GSH?
All 74AXP2G17GSH units undergo pre-shipment inspection (PSI). If there is an issue with 74AXP2G17GSH, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AXP2G17GSH part is unused and in its original packaging.
Return procedure for 74AXP2G17GSH:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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