Nexperia USA Inc. 74AXP2G3404GMH

Overview

74AXP2G3404 from Nexperia is a dual-function logic device integrating one Schmitt-trigger buffer (1A→1Y) and one Schmitt-trigger inverter (2A→2Y) in a single XSON6 package. It operates across 0.7 V to 2.75 V supply, delivers sub-2 ns propagation delay at 2.3–2.7 V, supports partial power-down via IOFF, and targets ultra-low-power portable and battery-powered signal conditioning applications.

For engineers reviewing the 74AXP2G3404 datasheet, 74AXP2G3404 pinout, 74AXP2G3404 application, or 74AXP2G3404 equivalent, key selection criteria include its dual-buffer/inverter functionality with Schmitt-trigger inputs, IOFF-enabled power-down isolation, sub-1.0 pF input capacitance, and guaranteed operation down to 0.7 V for energy-constrained systems.

Technical Context

This device implements two independent CMOS logic gates - one non-inverting buffer and one inverting gate - each with Schmitt-trigger input thresholds to tolerate slow-rising or noisy signals. Input hysteresis ensures robust noise immunity without external RC filtering.

Its IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current up to ±20 mA and enabling safe hot-insertion or partial system power-down. The design complies with JEDEC standards JESD8-12A.01 through JESD8-5A.01 across five voltage domains.

Key Specifications

Pinout & Package

XSON6 plastic extremely thin small outline package (SOT886), body size 1.0 × 1.45 × 0.5 mm, no leads, 6-terminal surface-mount construction with wettable flanks.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buffer/inverter applications.

Compared with 74LVC2G3404 and discrete LVC1G34+04 solutions, the 74AXP2G3404 uniquely combines sub-1 V operation, IOFF isolation, and 0.5 pF input capacitance in one XSON6 footprint - delivering superior power efficiency and board-space savings for battery-constrained designs.

Availability

74AXP2G3404 is available at Aetrix Electronics and suitable for IoT sensor nodes, wearable power sequencing, USB-C interface conditioning, and industrial HMI button debouncing requiring stable component supply across −40 °C to +85 °C.

Supply support for 74AXP2G3404 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for consumer, industrial, and automotive markets.

The AXP logic family targets ultra-low-power, multi-voltage digital interfacing - specifically engineered for energy-sensitive applications where sub-1 V operation and IOFF isolation are mandatory.

FAQ

Does the 74AXP2G3404 support true bidirectional signal routing?

No. It contains one unidirectional buffer (1A→1Y) and one unidirectional inverter (2A→2Y). Neither output can drive input pins, and there is no internal bus-hold or direction-control logic. The device functions strictly as two independent, input-to-output signal conditioners.

Can 74AXP2G3404 inputs safely accept 3.3 V signals when V_CC = 1.2 V?

Yes. Inputs tolerate voltages up to 2.75 V regardless of V_CC level, per Table 6 (VI max = +3.3 V absolute maximum, with current limiting). This allows safe interfacing with higher-voltage peripherals without external level shifters or clamping diodes.

What is the minimum load capacitance for which propagation delay is specified?

The datasheet specifies t_pd under test conditions with 5 pF load capacitance (Table 11). Figures 7–11 show t_pd variation down to 1 pF, confirming usable performance at sub-5 pF loads typical in short PCB traces or direct chip-to-chip connections.

How does IOFF behave when V_CC is ramping during power-up or power-down?

IOFF activates when V_CC drops below ~0.1 V and remains active until V_CC exceeds ~0.3 V. During this transition window, outputs enter high-impedance state with leakage ≤±0.5 µA (Table 8), preventing back-current flow even during incomplete power sequencing.