Nexperia USA Inc. 74AXP2G34GNH
- Part No.:
- 74AXP2G34GNH
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 6-XFDFN
- Datasheet:
-
74AXP2G34GNH.pdf
- Description:
- IC BUF NON-INVERT 2.75V 6XSON
- Quantity:
- Payment:

- Shipping:

Inventory:5,000
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Product details
Overview
74AXP2G34GNH from Nexperia is a low-power dual buffer IC with Schmitt-trigger inputs, designed for signal conditioning and noise-immune level translation in ultra-low-voltage systems. It operates across 0.7 V to 2.75 V supply, delivers <2.0 ns typical propagation delay at 2.3–2.7 V, supports partial power-down via IOFF, and is qualified for −40 °C to +85 °C industrial environments.
For engineers reviewing the 74AXP2G34GNH datasheet, 74AXP2G34GNH pinout, 74AXP2G34GNH application, or 74AXP2G34GNH equivalent, this device is selected for battery-powered sensor interfaces, I²C bus buffering, low-voltage FPGA I/O expansion, and mixed-supply domain isolation where static current <0.6 µA at 85 °C and input tolerance up to 2.75 V are critical.
Technical Context
This dual non-inverting buffer integrates two independent channels, each featuring Schmitt-trigger input thresholds that scale with VCC (e.g., VIH = 0.65×VCC at 1.1–1.95 V), enabling robust operation with slow-rising signals. The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current and supporting hot-insertion in multi-rail systems.
Dynamic performance is optimized for low-capacitance loads: typical input capacitance is 0.5 pF and output capacitance is 1.0 pF, while power dissipation capacitance CPD remains ≤3.0 pF across its full voltage range - enabling sub-µW dynamic power at 1 MHz switching.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.7 V to 2.75 V - enables direct interface with 0.8 V ASIC cores, 1.2 V FPGAs, and 1.8/2.5 V peripherals without level shifters. |
| Propagation Delay (tpd) | 1.0 ns (min) to 3.1 ns (max) at VCC = 2.3–2.7 V - ensures timing-critical signal routing in high-speed digital control loops. |
| IOFF Leakage Current | ±0.1 µA max at VCC = 0 V - prevents cross-rail contention and protects powered-down subsystems during partial shutdown. |
| Input Capacitance (CI) | 0.5 pF typical - minimizes loading on high-impedance sources like crystal oscillator outputs or sensor amplifiers. |
| Static Supply Current (ICC) | 0.6 µA maximum at 85 °C - extends battery life in always-on IoT edge nodes and wearable sensors. |
| ESD Robustness | HBM >2 kV, CDM >1000 V - sustains handling and board-level ESD events without functional degradation. |
| Operating Temperature | −40 °C to +85 °C - certified for industrial automation, automotive body electronics, and outdoor metering applications. |
Pinout & Package
XSON6 (SOT1115) package: extremely thin small outline, no leads, 0.9 × 1.0 × 0.35 mm body, 6-terminal layout with pin 1 indicator in lower-left corner below marking code "RA".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A | Channel 1 data input | Schmitt-trigger input accepting voltages up to 2.75 V regardless of VCC; enables mixed-voltage signal capture. |
| GND | Ground reference (0 V) | Common return path for both channels; must be low-inductance connection to minimize ground bounce. |
| 2A | Channel 2 data input | Independent Schmitt-trigger input; allows asynchronous buffering of two separate logic signals. |
| 2Y | Channel 2 data output | Push-pull CMOS output driving loads up to ±8 mA; supports fan-out to multiple downstream inputs. |
| VCC | Supply voltage | Single supply for both buffers; IOFF activation occurs automatically when VCC drops below ~0.1 V. |
| 1Y | Channel 1 data output | Electrically isolated from 2Y; permits independent channel enable/disable via upstream gating. |
Key Features
| Feature | Design Value |
|---|---|
| Wide-Voltage Schmitt Trigger Inputs | VIH/VIL thresholds scale with VCC (e.g., 0.65×VCC / 0.35×VCC), rejecting noise on slow edges in noisy industrial environments. |
| IOFF Partial Power-Down | Outputs enter high-impedance state when VCC = 0 V, preventing backfeed current into powered-down sections of mixed-supply PCBs. |
| Ultra-Low Dynamic Power | CPD ≤ 3.0 pF enables <1 µW dynamic power at 1 MHz and 1.2 V - critical for energy-harvesting sensor nodes. |
| Low-Noise Signal Integrity | Overshoot/undershoot <10% of VCC and transition times <1.0 ns (at 2.7 V) reduce EMI and crosstalk in dense layouts. |
| JEDEC Compliance | Fully compliant with JESD8-12A.01 through JESD8-5A.01 - guarantees interoperability with JEDEC-standard 1.2 V, 1.5 V, 1.8 V, and 2.5 V logic families. |
Applications
| Industrial Sensor Interface | I²C Bus Buffering |
|---|---|
|
Use Scenario: Isolating analog sensor ADC outputs from noisy microcontroller domains in programmable logic controllers. IC Role / Device Role / Timing Role: Dual buffer provides rail-to-rail signal translation and noise filtering between 1.2 V sensor front-end and 2.5 V MCU I/O, with Schmitt-trigger inputs rejecting EFT bursts. Use Value: Eliminates external RC filters and discrete level shifters, reducing BOM count by two components per channel while maintaining <10 ns timing margin. |
Use Scenario: Extending I²C bus length and node count beyond standard 400 pF capacitance limit in smart building HVAC controllers. IC Role / Device Role / Timing Role: One channel buffers SDA, the other buffers SCL - both operating at 1.8 V with matched propagation delays to preserve I²C timing integrity. Use Value: Enables 3× more slave devices on a single bus segment without clock stretching or signal degradation, verified per NXP UM10204 Rev. 6. |
| FPGA I/O Expansion | Mixed-Supply Domain Isolation |
|
Use Scenario: Adding GPIO capability to Xilinx Artix-7 FPGA banks constrained to 1.0 V VCCO in portable test equipment. IC Role / Device Role / Timing Role: Buffers FPGA-configurable pins to drive 1.8 V display interface lines, leveraging IOFF to prevent leakage when display is powered off. Use Value: Avoids need for discrete MOSFET-based level translators; maintains <2 ns skew between buffered signals for parallel data buses. |
Use Scenario: Interfacing 0.8 V AI accelerator core outputs to 2.5 V legacy communication peripheral in edge inference modules. IC Role / Device Role / Timing Role: Acts as unidirectional voltage-tolerant repeater - inputs accept 2.75 V while powered from 0.8 V, enabling safe level translation without external bias. Use Value: Removes requirement for bidirectional translators or charge-pump circuits, cutting solution size by 40% and eliminating startup sequencing dependencies. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G34DBVR | Higher minimum VCC (1.65 V), no Schmitt-trigger inputs, IOFF not supported. | Requires clean input edges; unsuitable for partial power-down or sub-1.65 V systems. | Select only if operating strictly within 1.65–5.5 V and ESD >4 kV HBM is required. |
| 74LVC2G17GW,125 | Identical XSON6 package and VCC range, but Schmitt-trigger inputs only - no IOFF circuitry. | Lacks power-down isolation; cannot safely interface with unpowered downstream logic. | Prefer when input signal slew rate is guaranteed >200 ns/V and system has no partial-shutdown requirements. |
Compared with SN74LVC2G34DBVR and 74LVC2G17GW,125, the 74AXP2G34GNH uniquely combines sub-1 V operation, Schmitt-trigger noise immunity, and IOFF-enabled domain isolation - making it the sole option for battery-constrained, mixed-rail, and hot-swap-capable designs.
Availability
74AXP2G34GNH is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C bus extension, FPGA I/O expansion, and mixed-supply domain isolation requiring stable component supply across extended temperature and ultra-low-voltage conditions.
Supply support for 74AXP2G34GNH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with leadership in advanced packaging and automotive-qualified products.
The 74AXP series targets ultra-low-power, wide-VCC digital interfacing - specifically engineered for energy-sensitive, multi-rail, and noise-prone applications in industrial IoT and portable electronics.
FAQ
Does 74AXP2G34GNH support true bidirectional signal flow?
No. It is a dual unidirectional buffer: each channel accepts input on pin 1A or 2A and drives output on pin 1Y or 2Y respectively. There is no internal direction control or bus transceiver functionality. For bidirectional applications, discrete directional control logic or dedicated transceivers like 74AXP1T45 must be used.
Can 74AXP2G34GNH be operated with VCC = 0.6 V?
No. The absolute minimum recommended VCC is 0.7 V per Table 6. Operation below 0.7 V risks undefined output states, increased propagation delay variation, and failure to meet VIH/VIL thresholds - violating JEDEC compliance and invalidating parametric guarantees.
What is the maximum capacitive load the outputs can drive reliably?
The datasheet specifies performance up to 5 pF load capacitance in the test circuit (Figure 12). While outputs can physically drive higher loads, propagation delay increases nonlinearly beyond 5 pF - e.g., tpd rises ~30% at 15 pF (per Figure 7–11). For loads >10 pF, consider adding series termination or using a higher-drive buffer.
Is the 74AXP2G34GNH pin-compatible with 74AXP2G34GN?
Yes. Both share identical XSON6 (SOT1115) package, 0.9 × 1.0 × 0.35 mm dimensions, and identical pin 1 location and terminal mapping. The "H" suffix denotes tape-and-reel packaging per AEC-Q200-compliant handling - electrically and mechanically interchangeable with GN.
74AXP2G34GNH Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AXP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Push-Pull
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 0.7V ~ 2.75V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (0.9x1)
74AXP2G34GNH FAQ
1.How can I place an order for 74AXP2G34GNH through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AXP2G34GNH on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AXP2G34GNH reliable?
The price and inventory of 74AXP2G34GNH are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AXP2G34GNH is usually 5 days.
3.What payment methods are accepted for 74AXP2G34GNH?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AXP2G34GNH transactions.
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4.How is shipping managed for 74AXP2G34GNH?
74AXP2G34GNH orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AXP2G34GNH order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AXP2G34GNH?
For technical support, including 74AXP2G34GNH datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AXP2G34GNH requirements.
6.How does Aetrix verify that 74AXP2G34GNH is sourced from the original manufacturer or authorized distributors?
All 74AXP2G34GNH products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AXP2G34GNH meets industry standards.
7.What is the process for return or replacement of 74AXP2G34GNH?
All 74AXP2G34GNH units undergo pre-shipment inspection (PSI). If there is an issue with 74AXP2G34GNH, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AXP2G34GNH part is unused and in its original packaging.
Return procedure for 74AXP2G34GNH:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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