Nexperia USA Inc. 74AXP2T3407GTX
- Part No.:
- 74AXP2T3407GTX
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN
- Datasheet:
-
74AXP2T3407GTX.pdf
- Description:
- IC TRANSLTR UNIDIRECTIONAL 8XSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74AXP2T3407 from Nexperia is a dual-supply, dual-channel level-translating buffer IC with one push-pull output (1Y) and one open-drain output (2Y), operating across independent VCCI (0.7–2.75 V) and VCCO (1.2–5.5 V) rails. It enables bidirectional voltage translation between sub-1V logic and 5V systems, features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and operates from −40 °C to +85 °C. Used in I²C bus interfacing, mixed-voltage microcontroller GPIO expansion, and low-power sensor hub signal conditioning.
For engineers reviewing the 74AXP2T3407 datasheet, 74AXP2T3407 pinout, 74AXP2T3407 application, or 74AXP2T3407 equivalent, key selection criteria include verified dual-rail voltage translation range, IOFF-enabled power sequencing compatibility, Schmitt-trigger input hysteresis, static current ≤0.5 µA at 85 °C, and open-drain output drive capability up to 12 mA at 4.5 V.
Technical Context
This device implements two independent buffer channels sharing dual supply domains: input logic referenced strictly to VCCI, outputs referenced strictly to VCCO. The 1Y output is CMOS push-pull with VOH ≥1.05 V at 1.2 V VCCO/−2 mA, while 2Y is true open-drain with no internal pull-up, supporting wired-AND and I²C-compatible signaling. Both inputs incorporate Schmitt-trigger thresholds (e.g., VIH = 0.65×VCCI for 1.1–1.95 V VCCI).
IOFF circuitry actively disables both outputs when either supply is at 0 V, limiting backflow current to ≤0.5 µA - critical for hot-swap and multi-rail power sequencing. Dynamic performance is characterized by propagation delay as low as 1.9 ns (VCCI=2.5 V, VCCO=5.0 V, Tamb=25 °C) and transition time ≤1.0 ns, with CPD of 0.4 pF (input) and 2.3–7.6 pF (output-dependent).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCCI Range | 0.7 V to 2.75 V: Enables interface with 0.8 V, 1.2 V, 1.8 V, and 2.5 V logic families on input side. |
| VCCO Range | 1.2 V to 5.5 V: Supports output connection to 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V systems without external level shifters. |
| IOFF Leakage | ≤0.5 µA at 85 °C: Ensures safe partial power-down during system sleep or rail sequencing without damaging back-current. |
| Input Capacitance | 0.6 pF typical: Minimizes capacitive loading on high-impedance or high-speed source drivers (e.g., MCU GPIOs). |
| Output Drive (2Y) | 12 mA sink at VCCO = 4.5 V: Sufficient for standard-mode I²C (400 kbps) with 1 kΩ pull-up and 400 pF bus capacitance. |
| Propagation Delay | 1.9 ns min (VCCI=2.5 V, VCCO=5.0 V): Enables use in timing-critical interconnect paths up to ~250 MHz toggle rate. |
| Static Current | ICCI ≤ 0.5 µA max at 85 °C; ICCO ≤ 1.8 µA max at 85 °C: Meets ultra-low-power requirements for battery-backed peripherals. |
Pinout & Package
Available in four compact packages: VSSOP8 (SOT765-1, 2.3 mm body width), XSON8 (SOT833-1, 1.0 × 1.95 × 0.5 mm), XSON8 (SOT1116, 1.2 × 1.0 × 0.35 mm), and XSON8 (SOT1203, 1.35 × 1.0 × 0.35 mm). All variants share identical pin numbering and terminal functions.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VCCI | Input domain supply rail; all input thresholds and leakage referenced to this voltage. |
| 2 | 1A | Buffer input for push-pull output 1Y; accepts voltages up to 2.75 V regardless of VCCI setting. |
| 3 | 2A | Buffer input for open-drain output 2Y; same Schmitt-trigger and voltage tolerance as 1A. |
| 4,5 | GND | Dual ground pins; must both be connected to 0 V for stable operation and ESD path integrity. |
| 6 | 2Y | Open-drain output; requires external pull-up to VCCO or another rail; supports wired-AND and I²C. |
| 7 | 1Y | CMOS push-pull output; actively drives HIGH/LOW to VCCO/GND; no external pull-up needed. |
| 10 | VCCO | Output domain supply rail; defines VOH/VOL levels and sink/source capability for both outputs. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent supply domains | VCCI (0.7–2.75 V) and VCCO (1.2–5.5 V) enable seamless translation between sub-1V IoT sensors and 5V industrial interfaces. |
| Schmitt-trigger inputs | Hysteresis ensures reliable switching with slow-rising signals (e.g., RC-filtered reset lines or long PCB traces) without oscillation. |
| IOFF partial power-down | Automatically disables outputs and limits leakage to ≤0.5 µA when either supply is off - eliminates need for external isolation switches. |
| Ultra-low dynamic capacitance | CI = 0.6 pF and CO(1Y) = 1.8 pF / CO(2Y) = 1.3 pF minimize signal distortion and crosstalk in dense routing. |
| JEDEC-compliant voltage standards | Fully compliant with JESD8-12A.01 through JESD12-6 across all supported VCCI/VCCO combinations for interoperability assurance. |
Applications
| Industrial Sensor Interface | I²C Bus Voltage Translation |
|---|---|
|
Use Scenario: Connecting 1.8 V MEMS pressure sensor to 3.3 V microcontroller ADC interface with shared ground. IC Role / Device Role / Timing Role: Translates sensor's 1.8 V digital enable and interrupt signals to 3.3 V logic levels while isolating supply domains. Use Value: Eliminates discrete MOSFET translators; IOFF prevents backfeed during sensor sleep mode; Schmitt inputs reject motor-drive EMI. |
Use Scenario: Interfacing 1.2 V FPGA I²C controller to 5 V EEPROM and 3.3 V temperature sensor on same bus. IC Role / Device Role / Timing Role: Provides bidirectional level shifting on SDA/SCL using 2Y open-drain outputs with external pull-ups. Use Value: Single device replaces dual discrete MOSFETs; 12 mA sink capability supports 400 kbps I²C with 30 cm trace length. |
| Low-Power Wearable Hub | Multi-Rail MCU GPIO Expansion |
|
Use Scenario: Expanding GPIO count of 0.8 V ultra-low-power BLE SoC to drive 2.5 V OLED display segments and 3.3 V LED indicators. IC Role / Device Role / Timing Role: Buffers SoC outputs via 1Y (push-pull) and 2Y (open-drain) to match display and indicator voltage requirements. Use Value: Static current <0.5 µA at 85 °C extends battery life; 0.6 pF input capacitance avoids degrading SoC's 10 MHz clock distribution. |
Use Scenario: Isolating and translating debug signals (SWDIO/SWCLK) between 1.1 V RISC-V core and 5 V JTAG emulator. IC Role / Device Role / Timing Role: Level-shifts bidirectional SWDIO using 2Y with external pull-up; clocks routed via 1Y with <2 ns delay. Use Value: Propagation delay variation <1 ns across VCCI/VCCO combinations ensures deterministic debug timing alignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-supply level translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TXB0102DGSR | Auto-direction sensing; higher ICCI (10 µA typ); no Schmitt inputs; VCCA/VCCB = 1.2–3.6 V only. | Requires no direction control signal but less robust against slow edges; unsuitable for >3.6 V output rails. | Select when bidirectional data flow (e.g., SPI MISO/MOSI) dominates and VCCO ≤3.6 V; avoid for I²C or noisy environments. |
| SN74AVCH2T45DCUR | Direction-controlled (DIR pin); lower VCCI min (0.65 V); higher CPD (12 pF); no IOFF circuitry. | Requires active DIR management; lacks power-down safety; higher dynamic load impacts high-speed timing margins. | Select when precise direction control is required and system guarantees synchronized power sequencing; not recommended for hot-swap. |
Compared with TXB0102DGSR and SN74AVCH2T45DCUR, the 74AXP2T3407 provides guaranteed Schmitt-trigger noise immunity, true IOFF protection for uncontrolled power sequencing, and full 5.5 V VCCO support - making it optimal for mixed-voltage industrial and automotive subsystems where reliability trumps auto-sensing convenience.
Availability
74AXP2T3407 is available at Aetrix Electronics and suitable for industrial sensor interfaces, I²C bus translation, low-power wearable hubs, and multi-rail MCU GPIO expansion requiring stable component supply across extended temperature and voltage ranges.
Supply support for 74AXP2T3407 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient components for automotive, industrial, computing, consumer, and communications markets.
The 74AXP2T3407 belongs to Nexperia's AXP ultra-low-power logic family, engineered specifically for voltage translation in battery-constrained and thermally sensitive applications where static current, IOFF safety, and Schmitt noise rejection are design-critical.
FAQ
Can 74AXP2T3407 translate from 2.5 V inputs to 5 V outputs?
Yes. With VCCI = 2.5 V and VCCO = 5.0 V, the device meets all specifications: VIH = 1.6 V (min), VOL ≤ 0.8 V at 12 mA sink, and propagation delay ≤ 1.6 ns. Input voltage tolerance up to 2.75 V ensures margin against overshoot. This configuration is validated per JESD8-5A.01 and JESD12-6 standards.
Does 74AXP2T3407 support I²C standard-mode (100 kbps) and fast-mode (400 kbps)?
Yes. The 2Y open-drain output sinks up to 12 mA at VCCO = 4.5 V, enabling reliable 400 kbps operation with standard 1 kΩ pull-ups and ≤400 pF total bus capacitance. Schmitt-trigger inputs reject noise on SCL/SDA, and IOFF prevents bus contention during power transitions - satisfying I²C electrical compliance requirements.
What happens if VCCI = 0 V while VCCO = 3.3 V is active?
The IOFF circuitry disables both 1Y and 2Y outputs, limiting output leakage to ≤0.5 µA. Inputs remain high-impedance, and no back-current flows into the powered VCCO rail. This behavior is tested per JESD78D Class II latch-up and ensures safe operation during asymmetric power sequencing common in modular systems.
Is the 74AXP2T3407 pin-compatible with older 74LVC2T45 variants?
No. While functionally similar, the 74AXP2T3407 uses an 8-pin layout with dedicated VCCI (pin 1), GND (pins 4,5), 2Y (pin 6), 1Y (pin 7), and VCCO (pin 10) - differing from LVC2T45's 10-pin TSSOP package and pin 10 = GND assignment. PCB redesign is required; migration requires validation of timing, leakage, and IOFF behavior.
74AXP2T3407GTX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74AXP
- Package/Case:
- 8-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- Open Drain
- Current - Output High, Low:
- 12mA, 12mA
- Voltage - Supply:
- 0.7V ~ 2.75V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON, SOT833-1 (1.95x1)
74AXP2T3407GTX FAQ
1.How can I place an order for 74AXP2T3407GTX through Aetrix?
Please submit a Request for Quotation (RFQ) for 74AXP2T3407GTX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74AXP2T3407GTX reliable?
The price and inventory of 74AXP2T3407GTX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74AXP2T3407GTX is usually 5 days.
3.What payment methods are accepted for 74AXP2T3407GTX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74AXP2T3407GTX transactions.
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4.How is shipping managed for 74AXP2T3407GTX?
74AXP2T3407GTX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74AXP2T3407GTX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74AXP2T3407GTX?
For technical support, including 74AXP2T3407GTX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74AXP2T3407GTX requirements.
6.How does Aetrix verify that 74AXP2T3407GTX is sourced from the original manufacturer or authorized distributors?
All 74AXP2T3407GTX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74AXP2T3407GTX meets industry standards.
7.What is the process for return or replacement of 74AXP2T3407GTX?
All 74AXP2T3407GTX units undergo pre-shipment inspection (PSI). If there is an issue with 74AXP2T3407GTX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74AXP2T3407GTX part is unused and in its original packaging.
Return procedure for 74AXP2T3407GTX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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