Nexperia USA Inc. 74CBTLV1G125GN,132

Overview

74CBTLV1G125GN,132 from Nexperia is a single high-speed CMOS bus switch with active-low output enable (OE), 5 Ω typical ON-resistance at 3.3 V, rail-to-rail signal switching, and IOFF partial power-down protection. It operates from 2.3 V to 3.6 V across –40 °C to +125 °C and is used in low-voltage data path isolation for portable computing and industrial I/O expansion.

For engineers reviewing the 74CBTLV1G125GN,132 datasheet, 74CBTLV1G125GN,132 pinout, 74CBTLV1G125GN,132 application, or 74CBTLV1G125GN,132 equivalent, key selection criteria include guaranteed sub-0.25 ns propagation delay at 3.3 V, <5 μA ICC supply current, Schmitt-trigger control input tolerance, IOFF-enabled backflow prevention during power sequencing, and XSON6 (SOT1115) package compatibility with 0.9 × 1.0 × 0.35 mm footprint constraints.

Technical Context

This device implements a single-pole, single-throw (SPST) analog/digital bus switch using CMOS transmission-gate architecture. The OE input controls conduction between bidirectional A and B ports, with Schmitt-trigger action on OE enabling robust operation under slow-rising control signals.

IOFF circuitry actively disables the switch and isolates I/O paths when VCC = 0 V, limiting backflow current to ±10 μA. The switch supports rail-to-rail voltage swing (0 V to VCC) on both A and B terminals and maintains ≤15 Ω maximum ON-resistance over full temperature and voltage range.

Key Specifications

Pinout & Package

XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal surface-mount device with 0.9 × 1.0 × 0.35 mm body dimensions and wettable flank capability for automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar bus switch applications.

Compared with SN74CBTLV1G125DBVR, the 74CBTLV1G125GN,132 delivers superior power sequencing safety and 15% lower RON; versus 74LVC1G3157GW,125, it offers tighter 3.3 V performance and 30% smaller footprint-critical for ultra-thin mobile designs.

Availability

74CBTLV1G125GN,132 is available at Aetrix Electronics and suitable for USB 2.0 isolation, industrial sensor hub multiplexing, and portable display data channel switching requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74CBTLV1G125GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET solutions optimized for efficiency-critical applications in automotive, industrial, and consumer electronics.

The 74CBTLV1G125GN,132 belongs to Nexperia's CBTLV (Configurable Bus Transceiver Low-Voltage) logic family, engineered specifically for low-latency, low-power signal routing in space-constrained, thermally demanding environments.

FAQ

What is the recommended pull-up resistor value for the OE pin?

The minimum pull-up resistor value depends on the current-sinking capability of the driver controlling OE. For standard CMOS drivers with 4 mA sink capability at 3.3 V, a 10 kΩ resistor ensures OE remains solidly HIGH during power-up while limiting current to <330 μA. Lower values (e.g., 4.7 kΩ) improve noise immunity in electrically noisy environments but increase static power draw.

Can the 74CBTLV1G125GN,132 switch analog signals such as audio or sensor outputs?

Yes-the device supports rail-to-rail analog signal switching up to its specified bandwidth (263 MHz at –3 dB). Its 10.3 pF ON-state capacitance, <0.1% THD+N at 1 kHz, and flat RON across 0–3.3 V make it suitable for line-level audio routing and DC-coupled sensor interfaces where signal fidelity and low distortion are required.

Does the n.c. pin (Pin 5) require any PCB layout treatment?

No-Pin 5 is a true no-connect terminal with no internal bond wire or silicon connection. It may be left floating or tied to GND for mechanical stability, but must never be connected to VCC or any active signal. No thermal relief or solder mask opening is required beyond standard XSON6 pad design rules.

How does IOFF behavior differ from standard high-impedance OFF-state?

Standard high-Z OFF-state relies on gate bias to block current but fails when VCC = 0 V and external voltage is applied to A/B ports-causing destructive backflow. IOFF uses dedicated circuitry that actively disables the switch transistors regardless of VCC level, limiting leakage to ±10 μA even with 3.6 V applied to A/B while VCC = 0 V.