Nexperia USA Inc. 74CBTLV1G125GW-Q1H

Overview

74CBTLV1G125GW-Q1H from Nexperia is a single-channel, automotive-qualified bus switch IC with active-low output enable control, 5 Ω typical ON-resistance at 3.3 V, rail-to-rail signal switching, and IOFF partial power-down protection. It operates from 2.3 V to 3.6 V across –40 °C to +125 °C and is used in high-speed data path isolation for infotainment serial buses and ADAS sensor interfaces.

For engineers reviewing the 74CBTLV1G125GW-Q1H datasheet, 74CBTLV1G125GW-Q1H pinout, 74CBTLV1G125GW-Q1H application, or 74CBTLV1G125GW-Q1H equivalent, key selection criteria include guaranteed low RON over temperature, AEC-Q100 Grade 1 qualification, IOFF-enabled system-level power sequencing, and Schmitt-trigger input tolerance for noisy automotive environments.

Technical Context

This device implements a single-pole, single-throw (SPST) analog bus switch with complementary MOSFET topology, enabling bidirectional signal flow between ports A and B when OE is logic LOW. The internal switch uses CMOS transmission-gate architecture with matched P/N devices to achieve rail-to-rail voltage handling and minimal distortion.

IOFF circuitry actively disables the switch and isolates I/O terminals when VCC = 0 V, limiting backflow current to ±10 μA. Schmitt-trigger inputs on OE provide hysteresis of ~0.3 V (at VCC = 3.3 V), ensuring robust operation with slow-rising control signals common in microcontroller GPIO outputs.

Key Specifications

Pinout & Package

TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm pitch, lead-free and RoHS compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar bus switch applications.

Compared with SN74CBTLV1G125QDRYRQ1, the 74CBTLV1G125GW-Q1H offers superior CDM ESD resilience and verified IOFF behavior at zero supply, making it more suitable for harsh automotive harness environments; versus 74LVC1G3157GW-Q100, it delivers lower RON and simpler control for dedicated bus gating, reducing BOM count and layout area.

Availability

74CBTLV1G125GW-Q1H is available at Aetrix Electronics and suitable for automotive infotainment, ADAS camera interface, and body control module applications requiring stable component supply, AEC-Q100 compliance, and long-term lifecycle support.

Supply support for 74CBTLV1G125GW-Q1H includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and discrete components, with leadership in automotive-qualified standard products.

The 74CBTLV1G125GW-Q1H belongs to Nexperia's automotive logic bus switch family, designed specifically for signal path isolation and power-domain boundary management in modern vehicle ECUs.

FAQ

What is the maximum allowable voltage on the A or B port when VCC = 0 V?

The absolute maximum switch voltage rating is –0.5 V to VCC + 0.5 V. When VCC = 0 V, this permits –0.5 V to +0.5 V on A/B ports. Exceeding this risks latch-up or permanent damage, as IOFF protection does not extend beyond these limits. System design must ensure external clamping or biasing stays within this window during power-off states.

Can OE be driven directly from a 1.8 V microcontroller GPIO without level shifting?

No. VIH minimum is 2.0 V at VCC ≥ 2.7 V, and VIH scales with supply - at VCC = 2.3 V, VIH min is 1.7 V. A 1.8 V GPIO may not reliably assert HIGH on OE, risking undefined switch state. A resistor divider or level shifter is required to ensure OE sees ≥2.0 V for guaranteed disable functionality across temperature and process variation.

How does the 5 Ω ON-resistance affect signal integrity in a 100 MHz SPI clock line?

With 10.3 pF switch capacitance and 5 Ω RON, the RC time constant is ~52 ps - negligible versus a 5 ns SPI clock period. Measured propagation delay is 0.16 ns, contributing <0.3% timing uncertainty. No measurable duty cycle distortion or edge degradation occurs at 100 MHz, provided trace impedance remains controlled and load capacitance is ≤30 pF.

Is the GND pin (pin 3) internally connected to the substrate or thermal pad?

Per SOT353-1 package construction and Nexperia's thermal characterization, pin 3 (GND) is the sole electrical and thermal connection to the die substrate. There is no exposed thermal pad; heat dissipation relies entirely on the leadframe via pin 3 and adjacent leads. PCB layout must assign a low-impedance copper pour directly to pin 3 for optimal thermal performance at 250 mW Ptot.