Texas Instruments 74CBTLV3126RGYRG4
- Part No.:
- 74CBTLV3126RGYRG4
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 14-VFQFN Exposed Pad
- Datasheet:
-
74CBTLV3126RGYRG4.pdf
- Description:
- IC BUS SWITCH 1 X 1:1 14VQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74CBTLV3126RGYRG4 from Texas Instruments is a low-voltage quadruple FET bus switch with independent 5Ω analog switches, rail-to-rail signal switching, and Ioff partial-power-down protection. It operates from 2.3V to 3.6V, supports –40°C to +85°C ambient, and isolates ports when powered off-used in JTAG/SPI signal routing and hot-swap isolation in enterprise computing and wired networking systems.
For engineers reviewing the 74CBTLV3126RGYRG4 datasheet, 74CBTLV3126RGYRG4 pinout, 74CBTLV3126RGYRG4 application, or 74CBTLV3126RGYRG4 equivalent, key selection criteria include on-resistance (5–8Ω), Ioff leakage (<10µA at VCC = 0), thermal performance (RθJA = 101.8°C/W), and VQFN-14 package compatibility with high-density PCB layouts.
Technical Context
The 74CBTLV3126RGYRG4 implements four independent bidirectional FET switches, each controlled by a dedicated active-high output-enable (OE) input. Switch conduction is governed by MOSFET channel resistance, not logic-level translation, enabling true rail-to-rail analog pass-through without level shifting.
Its Ioff architecture blocks backflow current when VCC = 0, ensuring system-level isolation during power sequencing or partial shutdown-critical for live-insertion applications. The device exhibits latch-up immunity exceeding 100mA per JESD78 Class II and supports 30pF load capacitance with sub-nanosecond propagation delay (tpd ≤ 0.25ns at VCC = 3.3V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| On-resistance (ron) | 5–8Ω typical at VCC = 3.3V, 64mA - ensures minimal voltage drop and signal attenuation across switched data paths |
| Ioff leakage | <10µA at VCC = 0, VI/VO = 0–3.6V - enables safe partial-power-down operation without damaging back-current |
| Supply voltage range | 2.3V to 3.6V - compatible with 2.5V and 3.3V logic domains and mixed-voltage board designs |
| Operating temperature | –40°C to +85°C - validated for industrial-grade deployment in enterprise servers and networking equipment |
| Propagation delay (tpd) | ≤0.25ns at VCC = 3.3V - preserves signal integrity for high-speed digital buses up to 1GHz effective bandwidth |
| ESD rating (HBM) | ±2000V - meets JEDEC JS-001 for robust handling in automated assembly and field service environments |
| Thermal resistance (RθJA) | 101.8°C/W (VQFN-14) - supports continuous operation at full load without external heatsinking in compact enclosures |
Pinout & Package
VQFN-14 (RGY) package: 4.00mm × 3.50mm body, 0.5mm pitch, exposed thermal pad (optional GND connection). Pin 1 marked via top-side dot; thermal pad not required for soldering but improves thermal performance if connected to GND plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE, 3OE, 4OE | Active-high enable inputs | Each independently controls one switch pair; OE = low disables A↔B path, forcing high-impedance isolation |
| 1A–4A, 1B–4B | Bidirectional I/O channels | Pass analog/digital signals rail-to-rail with no directionality constraint; A and B are functionally identical terminals |
| VCC | Power supply | Single 2.3–3.6V supply powers all four switches and internal control circuitry |
| GND | Ground reference | Common return path for supply and signal references; must be low-impedance for noise immunity |
| Thermal Pad | Exposed copper pad | Improves thermal dissipation when soldered to inner-layer GND plane; floating connection permitted |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail analog switching | Supports full 0V to VCC signal swing on all I/O ports-enables transparent pass-through of GPIO, SPI clock/data, and JTAG TCK/TMS without level-shifting circuitry |
| Ioff partial-power-down protection | Blocks >99.9% of backflow current when VCC = 0, eliminating need for external power sequencing in hot-swap modules and modular backplanes |
| 5Ω low on-resistance | Minimizes insertion loss and timing skew across high-speed control lines-critical for maintaining setup/hold margins in 100+MHz digital interfaces |
| Standard 126-type pinout | Pin-compatible with legacy 74-series bus switches (e.g., SN74LVC1G3157), simplifying drop-in upgrades in existing designs |
| Latch-up immunity | Exceeds 100mA per JESD78 Class II-ensures reliability in noisy industrial environments with transient voltage coupling |
Applications
| Server Backplane Signal Routing | JTAG Debug Isolation |
|---|---|
Use Scenario: Isolating PCIe configuration lanes and SMBus management signals between CPU and hot-pluggable mezzanine cards in 1U rack servers. IC Role / Device Role / Timing Role: Bidirectional analog switch providing signal path enable/disable under BMC control; maintains timing-critical trace impedance continuity during insertion/removal. Use Value: Eliminates manual power sequencing steps and prevents bus contention during live card replacement-reducing mean time to repair (MTTR) by >40%. | Use Scenario: Multiplexing JTAG TDI/TDO/TCK/TMS lines between multiple ASICs on a shared debug header in multi-core SoC test fixtures. IC Role / Device Role / Timing Role: Independent channel switch enabling per-device JTAG access without physical re-wiring; supports IEEE 1149.1 boundary-scan compliance. Use Value: Reduces test fixture complexity and eliminates cross-talk-induced false fails during production ICT-cutting test cycle time by 22%. |
| SPI Flash Memory Sharing | Industrial PLC I/O Expansion |
Use Scenario: Allowing two microcontrollers to share a single quad-SPI flash memory device in redundant controller architectures for factory automation HMIs. IC Role / Device Role / Timing Role: Quad-channel analog switch routing SCLK, IO0–IO3, and HOLD# signals; maintains signal edge rates and drive strength across both masters. Use Value: Avoids dual-flash duplication cost while preserving deterministic boot timing-reducing BOM cost by $1.85/unit at 100k volume. | Use Scenario: Adding isolated digital input/output expansion to a base PLC controller via DIN-rail mounted I/O modules with independent power domains. IC Role / Device Role / Timing Role: Signal-level isolation switch enabling safe GPIO sharing between 24V field-side and 3.3V logic-side circuits during module hot-swap. Use Value: Prevents ground-loop induced noise and protects main controller from transients-extending field reliability beyond 15 years MTBF. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FET bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTLV3245RGYR | Octal (8-channel), 5.5Ω ron, same VCC range and Ioff spec - larger pin count (24-pin VQFN), higher channel density | Used where 8-channel consolidation reduces component count vs. two 74CBTLV3126RGYRG4 units | Select when board space is constrained and full octal functionality is needed; requires layout revision due to different footprint and pinout |
| 74LVC1G3157DCKR | Single-channel, 6Ω ron, same 5-pin SC70 package - lower integration, no multi-OE control, limited to point-to-point isolation | Preferred for discrete signal gating (e.g., single reset line) rather than quad-bus routing | Choose for minimal-footprint, low-cost gating of individual control lines; not suitable for parallel bus isolation |
Compared with SN74CBTLV3245RGYR and 74LVC1G3157DCKR, the 74CBTLV3126RGYRG4 uniquely balances quad-channel density, 14-pin VQFN compactness, and independent OE control-making it optimal for mid-complexity signal routing where channel granularity and layout efficiency are both critical.
Availability
74CBTLV3126RGYRG4 is available at Aetrix Electronics and suitable for enterprise server backplanes, JTAG debug multiplexers, SPI flash sharing architectures, and industrial PLC I/O expansion requiring stable component supply and long-term lifecycle support.
Supply support for 74CBTLV3126RGYRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 90 years of innovation in industrial, automotive, and communications markets.
The CBTLV logic family-including the 74CBTLV3126RGYRG4-is engineered for low-voltage, high-speed bus switching in dense, thermally constrained systems where signal integrity, power sequencing resilience, and small-form-factor packaging are essential.
FAQ
What is the maximum continuous current rating per channel for the 74CBTLV3126RGYRG4?
The 74CBTLV3126RGYRG4 supports a maximum continuous channel current of 128mA per I/O path, verified across the full operating temperature range (–40°C to +85°C) and supply voltage (2.3V–3.6V). This rating applies to both A and B terminals simultaneously under DC or steady-state AC conditions, and is defined in Section 5.1 Absolute Maximum Ratings of the TI datasheet SCDS038N. Exceeding this limit risks thermal runaway or permanent on-resistance degradation in the 74CBTLV3126RGYRG4.
Does the 74CBTLV3126RGYRG4 require external pull-up or pull-down resistors on its OE pins?
Yes-the 74CBTLV3126RGYRG4 OE pins must be actively driven to a defined logic state (VCC or GND) to prevent floating inputs that could cause unintended switch activation. TI recommends using a pull-down resistor to GND on each OE pin during power-up/power-down to guarantee high-impedance isolation; minimum resistance value depends on the driver's current-sinking capability. Leaving OE pins unconnected violates Recommended Operating Conditions and may result in undefined behavior in the 74CBTLV3126RGYRG4.
Can the 74CBTLV3126RGYRG4 operate with 1.8V logic signals while powered from a 3.3V supply?
Yes-the 74CBTLV3126RGYRG4 supports rail-to-rail signal switching, meaning it passes 0V to VCC (3.3V) signals without attenuation or distortion. Input signals as low as 0V or as high as 3.3V are fully compatible, including 1.8V logic levels, because the FET switch operates in ohmic mode-not as a logic gate. The 74CBTLV3126RGYRG4 does not perform level translation, but its low on-resistance (5–8Ω) preserves signal fidelity for mixed-voltage interfaces like 1.8V MCU GPIO controlling 3.3V peripherals.
What is the thermal pad connection requirement for the 74CBTLV3126RGYRG4 in VQFN-14 (RGY) package?
The exposed thermal pad on the 74CBTLV3126RGYRG4 VQFN-14 package has no electrical requirement: it may be left floating or connected to GND. TI states "There is no requirement to solder this pad"; however, soldering it to a PCB GND plane significantly improves thermal performance-reducing RθJA from 101.8°C/W to ~41.6°C/W (RθJB) and enhancing power handling in sustained high-current operation. For reliability-critical applications, GND connection is strongly advised, but not mandatory for basic functionality of the 74CBTLV3126RGYRG4.
How does the Ioff feature of the 74CBTLV3126RGYRG4 protect downstream circuitry during partial power-down?
The Ioff feature in the 74CBTLV3126RGYRG4 disables internal conduction paths when VCC = 0V, limiting leakage current to <10µA even if up to 3.6V is present on any I/O pin. This prevents damaging backflow current from externally powered subsystems (e.g., a live backplane) into a powered-down controller domain-eliminating the need for external blocking diodes or complex power sequencing. The 74CBTLV3126RGYRG4 achieves this via integrated FET gate biasing that forces cutoff regardless of I/O voltage polarity, ensuring robust isolation in hot-swap and modular system architectures.
74CBTLV3126RGYRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTLV
- Package/Case:
- 14-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Type:
- Bus Switch
- Circuit:
- 1 x 1:1
- Independent Circuits:
- 4
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-VQFN (3.5x3.5)
74CBTLV3126RGYRG4 FAQ
1.How can I place an order for 74CBTLV3126RGYRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74CBTLV3126RGYRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74CBTLV3126RGYRG4 reliable?
The price and inventory of 74CBTLV3126RGYRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74CBTLV3126RGYRG4 is usually 5 days.
3.What payment methods are accepted for 74CBTLV3126RGYRG4?
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4.How is shipping managed for 74CBTLV3126RGYRG4?
74CBTLV3126RGYRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74CBTLV3126RGYRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74CBTLV3126RGYRG4?
For technical support, including 74CBTLV3126RGYRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74CBTLV3126RGYRG4 requirements.
6.How does Aetrix verify that 74CBTLV3126RGYRG4 is sourced from the original manufacturer or authorized distributors?
All 74CBTLV3126RGYRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74CBTLV3126RGYRG4 meets industry standards.
7.What is the process for return or replacement of 74CBTLV3126RGYRG4?
All 74CBTLV3126RGYRG4 units undergo pre-shipment inspection (PSI). If there is an issue with 74CBTLV3126RGYRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74CBTLV3126RGYRG4 part is unused and in its original packaging.
Return procedure for 74CBTLV3126RGYRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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