Nexperia USA Inc. 74CBTLV3384BQ,118

Overview

74CBTLV3384BQ,118 from Nexperia is a 10-bit dual-bus switch with independent 5-bit output enables (1OE/2OE), designed for high-speed bidirectional signal routing in low-voltage digital systems. It features 5 Ω typical ON-resistance, rail-to-rail switching across 2.3 V–3.6 V supply, and IOFF partial power-down protection. Used in PCIe Gen1/2 interconnect buffering, memory address/data bus isolation, and FPGA I/O expansion.

For engineers reviewing the 74CBTLV3384BQ,118 datasheet, 74CBTLV3384BQ,118 pinout, 74CBTLV3384BQ,118 application, or 74CBTLV3384BQ,118 equivalent, key selection criteria include guaranteed sub-5 ns enable/disable timing at 3.3 V, ±100 μA max ICC at 3.6 V, -40 °C to +125 °C operation, Schmitt-trigger control inputs, and DHVQFN24 thermal-enhanced package compatibility with high-density PCB layouts.

Technical Context

This device implements two independent 5-channel single-pole single-throw (SPST) analog bus switches, each controlled by an active-low enable input (1OE or 2OE). Switch conduction is bidirectional with no internal directionality-data flows equally well from A to B or B to A when enabled.

IOFF circuitry actively disables all channels and limits backflow current to ±50 μA when VCC = 0 V, enabling hot-swap and partial power-down system architectures. Schmitt-trigger inputs tolerate slow-rising control signals down to 200 ns/V transition rate, eliminating external RC filtering in noisy environments.

Key Specifications

Pinout & Package

DHVQFN24 (SOT815-1) package: 3.5 × 5.5 × 0.85 mm body, 24-terminal quad flat no-lead with exposed thermal pad (non-soldered or floating GND connection recommended).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar bus switch applications.

Compared with SN74CBT3384CPWR and 74LVC1G3157GW,125, the 74CBTLV3384BQ,118 uniquely delivers dual 5-bit independent control, guaranteed IOFF, and DHVQFN24 thermal performance - making it optimal for space-constrained, multi-rail industrial controllers requiring deterministic power sequencing.

Availability

74CBTLV3384BQ,118 is available at Aetrix Electronics and suitable for PCIe interconnect buffering, FPGA I/O expansion, memory bus isolation, and industrial CAN/LIN interface multiplexing requiring stable component supply across extended temperature ranges.

Supply support for 74CBTLV3384BQ,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74CBTLV series targets low-voltage, high-speed digital interface applications - specifically engineered for minimal propagation delay, ultra-low ON-resistance, and robust partial power-down behavior in dense PCB layouts.

FAQ

What is the maximum allowable load capacitance for maintaining specified tpd and RON?

The datasheet specifies dynamic testing with 30 pF (2.3–2.7 V) and 50 pF (3.0–3.6 V) loads. At 50 pF and 3.3 V, tpd remains ≤0.20 ns and RON stays ≤7.0 Ω. Exceeding 50 pF increases propagation delay nonlinearly due to RC time constant effects - design verification with actual board parasitics is recommended above this threshold.

Can 1OE and 2OE be tied together for unified 10-bit control?

Yes - connecting 1OE and 2OE simplifies control to a single enable line, converting the device into a 10-bit bus switch. This configuration maintains all specifications including RON, tpd, and IOFF, but forfeits independent gating of the two 5-bit banks. No additional pull-up/down resistors are needed due to CMOS input structure.

Is the exposed thermal pad on the DHVQFN24 package required to be soldered?

No - the thermal pad (terminal 1 index area) has no electrical function and may remain unsoldered. If soldered, it must be left floating or connected to GND; no thermal vias or copper pour are mandatory. Thermal performance meets spec without pad connection, though soldering improves θJA by ~15 °C/W in high-power scenarios.

Does the device support hot insertion when VCC is ramping?

Yes - IOFF functionality activates automatically when VCC drops below ~0.8 V, limiting back-current to ±50 μA even during partial power-up. Combined with Schmitt-trigger inputs, this allows reliable hot-insertion into live backplanes where VCC ramps independently of control signals, provided VI remains within -0.5 V to VCC + 0.5 V limits.