Renesas 74CBTLV3384PGG
- Part No.:
- 74CBTLV3384PGG
- Manufacturer:
- Renesas
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74CBTLV3384PGG.pdf
- Description:
- IC BUS SWITCH 5 X 1:1 24TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,082
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74CBTLV3384PGG from Renesas Electronics is a low-voltage 10-bit bi-directional bus switch IC with dual 5-bit configuration, 5Ω typical on-state resistance (RON), 0.25 ns max propagation delay at 3.3V, and operation across –40°C to +85°C industrial temperature range. It enables high-speed 3.3V bus isolation and switching in memory expansion and data path routing applications.
For engineers reviewing the 74CBTLV3384PGG datasheet, 74CBTLV3384PGG pinout, 74CBTLV3384PGG application, or 74CBTLV3384PGG equivalent, key selection criteria include VCC range (2.3–3.6V), OE-controlled dual 5-bit switching, over-voltage tolerance up to 4.6V, and TSSOP-24 package compatibility with high-density PCB layouts.
Technical Context
The 74CBTLV3384PGG implements two independent 5-bit bus switches, each controlled by its own active-low output-enable (1OE, 2OE) input. Switching is fully bi-directional with no direction pin required, and the device maintains high-impedance isolation when powered down or OE is high.
Its architecture supports rail-to-rail signal pass-through with minimal distortion: RON is specified at 5–40Ω depending on voltage and current conditions, and tPD remains ≤0.25 ns at 3.3V with 50 pF load. Input clamping and >200V machine-model ESD protection ensure robustness in noisy industrial environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.3V to 3.6V - Enables direct interface with 2.5V/3.3V logic without level shifters |
| RON (Typ) | 5Ω at VCC = 3V, IO = 24mA - Minimizes voltage drop and signal attenuation in high-speed data paths |
| tPD (Max) | 0.25 ns at VCC = 3.3V - Supports >1 GHz effective switching rates for DDR and parallel bus applications |
| IOFF (Max) | 50 µA at VCC = 0 - Ensures true isolation during power sequencing or hot-swap events |
| VI/O Tolerance | –0.5V to +4.6V - Allows safe interfacing with mixed-voltage systems (e.g., 5V-tolerant I/O on 3.3V supply) |
| Operating Temp | –40°C to +85°C - Qualified for industrial control, networking, and embedded computing environments |
| ESD Rating | 2000V HBM, 200V MM - Meets MIL-STD-883 requirements for board-level reliability |
Pinout & Package
TSSOP-24 (PGG24) package: 7.8 mm × 4.4 mm body, 0.65 mm pitch, exposed pad not present, RoHS-compliant green molding compound.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 22 | GND | Power return reference for both switch banks and control logic |
| 2–6, 11–15 | 1A1–1A5 / 1B1–1B5 | First 5-bit bidirectional data port (A↔B); no direction control needed |
| 7, 21 | 1OE / 2OE | Active-low enable inputs - tie to VCC via pull-up for power-up high-Z safety |
| 8–10, 16–20 | 2A1–2A5 / 2B1–2B5 | Second 5-bit bidirectional data port (A↔B); electrically isolated from first bank |
| 24 | VCC | Single 2.3–3.6V supply for all logic and analog switch functions |
Key Features
| Feature | Design Value |
|---|---|
| Bi-directional low-RON switch | 5Ω typical on-resistance enables <10 mV drop at 2 mA, preserving signal integrity in 3.3V buses |
| Power-off isolation | IOFF ≤ 50 µA ensures zero current leakage between ports when VCC = 0 - critical for hot-plug and power-gating |
| Over-voltage tolerant I/O | Withstands –0.5V to +4.6V on all A/B pins regardless of VCC state - eliminates need for external clamping diodes |
| Dual independent 5-bit control | Separate 1OE and 2OE inputs allow asymmetric enable timing and partial bus activation without software coordination |
| Industrial temperature support | Guaranteed operation from –40°C to +85°C with no derating - validated for factory automation and telecom infrastructure |
Applications
| Memory Expansion Interface | PCI/PCIe Slot Isolation |
|---|---|
Use Scenario: Adding SRAM or Flash memory to microcontroller-based industrial controllers with limited address/data bus pins. IC Role / Device Role / Timing Role: Bidirectional 10-bit bus switch enabling dynamic connection/disconnection of memory banks under firmware control. Use Value: Eliminates bus contention during memory remapping; 0.25 ns tPD avoids timing violations in 100 MHz+ parallel interfaces. | Use Scenario: Isolating legacy PCI add-in cards from host system during hot-swap or fault recovery sequences. IC Role / Device Role / Timing Role: Dual 5-bit switch providing independent enable control for address/control and data lanes. Use Value: Prevents back-driving of powered-down slots; 5Ω RON maintains signal rise/fall times within PCI spec limits. |
| Multi-Processor Data Sharing | FPGA Configuration Bus Routing |
Use Scenario: Sharing peripheral resources (e.g., ADC, UART) between two ARM Cortex-M cores on a single PCB. IC Role / Device Role / Timing Role: 10-bit bidirectional switch acting as a hardware-multiplexed data path with OE-driven arbitration. Use Value: Enables deterministic, glitch-free handoff between processors; no clock domain crossing logic required. | Use Scenario: Dynamically routing JTAG or slave-serial configuration signals between multiple FPGAs sharing a common programming header. IC Role / Device Role / Timing Role: Low-capacitance (7 pF CIO(OFF)) switch isolating unused FPGA configuration ports during boot. Use Value: Reduces configuration signal crosstalk and ensures reliable bitstream loading across heterogeneous FPGA families. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTLV3384PWR | Same 10-bit dual-switch function, identical RON/tPD specs, but TI's version uses 0.65 mm pitch TSSOP-24 (PW package) with different thermal pad design | Pinout-compatible but requires verification of solder mask and stencil design due to minor footprint variations | Select when sourcing from TI-authorized channels or requiring TI-specific qualification documentation |
| 74LVC1G3157GW | Single-pole double-throw (SPDT) 1-bit switch only; 6Ω RON, 0.2 ns tPD, but lacks multi-bit integration and dual-OE control | Suitable only for point-to-point signal routing, not parallel bus isolation | Choose only for ultra-low-pin-count designs where discrete 1-bit switching suffices and board space permits 5× separate devices |
Compared with SN74CBTLV3384PWR and 74LVC1G3157GW, the 74CBTLV3384PGG uniquely delivers integrated dual 5-bit switching with industrial temp rating and over-voltage tolerance in a single TSSOP-24 package - reducing component count and interconnect complexity in 3.3V bus architectures.
Availability
74CBTLV3384PGG is available at Aetrix Electronics and suitable for industrial control systems, network interface cards, and FPGA-based prototyping platforms requiring stable component supply and long-term manufacturability.
Supply support for 74CBTLV3384PGG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and connectivity solutions for automotive, industrial, and data infrastructure markets.
The CBTLV family was designed specifically for high-speed, low-voltage bus switching in 2.5V/3.3V digital systems - emphasizing minimal propagation delay, rail-to-rail signal fidelity, and robust power sequencing behavior.
FAQ
What is the maximum operating voltage on the A/B pins of the 74CBTLV3384PGG when VCC = 0V?
The 74CBTLV3384PGG supports –0.5V to +4.6V on all A and B terminals regardless of VCC state. This over-voltage tolerance allows safe connection to live 5V buses while the device is unpowered, preventing latch-up and enabling hot-swap capability without external protection components. The specification is verified per absolute maximum ratings in the Renesas datasheet DSC-5742/7.
Does the 74CBTLV3384PGG require external pull-up resistors on OE pins, and if so, what value is recommended?
Yes - to guarantee high-impedance state during power-up/power-down, 1OE and 2OE must be tied to VCC via pull-up resistors. The minimum value depends on the driver's sink capability; Renesas recommends ≥10 kΩ for standard CMOS drivers. Lower values (e.g., 4.7 kΩ) improve noise immunity but increase static current. The 74CBTLV3384PGG datasheet specifies this requirement in the "Power-Up Sequence" section.
Can the 74CBTLV3384PGG be used to isolate I²C bus lines?
No - the 74CBTLV3384PGG is not suitable for I²C isolation because it lacks built-in bus-hold or weak pull-up functionality and does not support open-drain signaling. Its low RON creates a direct conductive path that would short SDA/SCL lines when enabled, violating I²C electrical specifications. For I²C, dedicated level translators like PCA9306 or TXS0108E are required instead of the 74CBTLV3384PGG.
What is the thermal resistance (θJA) of the 74CBTLV3384PGG in its TSSOP-24 package?
The 74CBTLV3384PGG TSSOP-24 (PGG24) package has a typical junction-to-ambient thermal resistance (θJA) of 120°C/W under standard JEDEC 2-layer board conditions (1-inch² copper). This value assumes no internal thermal pad and standard solder mask-defined pads. Actual θJA may vary ±15% based on PCB layout; Renesas provides detailed thermal characterization in Application Note AN-xxxx (Rev. 2019).
Is the 74CBTLV3384PGG pin-compatible with the older 74CBT3384 variant?
No - the 74CBTLV3384PGG is not pin-compatible with the 74CBT3384. While both are 10-bit bus switches in 24-pin packages, the 74CBT3384 uses QSOP-24 (PCG24) or SOIC-24 and operates at 4.5–5.5V, whereas the 74CBTLV3384PGG is optimized for 2.3–3.6V and packaged exclusively in TSSOP-24 (PGG24). Pin functions differ in control logic thresholds and absolute max ratings, making direct substitution unsafe without redesign.
74CBTLV3384PGG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- 74CBTLV
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 5 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
74CBTLV3384PGG FAQ
1.How can I place an order for 74CBTLV3384PGG through Aetrix?
Please submit a Request for Quotation (RFQ) for 74CBTLV3384PGG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74CBTLV3384PGG reliable?
The price and inventory of 74CBTLV3384PGG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74CBTLV3384PGG is usually 5 days.
3.What payment methods are accepted for 74CBTLV3384PGG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74CBTLV3384PGG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74CBTLV3384PGG?
74CBTLV3384PGG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74CBTLV3384PGG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74CBTLV3384PGG?
For technical support, including 74CBTLV3384PGG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74CBTLV3384PGG requirements.
6.How does Aetrix verify that 74CBTLV3384PGG is sourced from the original manufacturer or authorized distributors?
All 74CBTLV3384PGG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74CBTLV3384PGG meets industry standards.
7.What is the process for return or replacement of 74CBTLV3384PGG?
All 74CBTLV3384PGG units undergo pre-shipment inspection (PSI). If there is an issue with 74CBTLV3384PGG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74CBTLV3384PGG part is unused and in its original packaging.
Return procedure for 74CBTLV3384PGG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74CBTLV3384PGG Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

