Nexperia USA Inc. 74CBTLVD3384BQ,118

Overview

74CBTLVD3384BQ,118 from Nexperia is a 10-bit dual 5-channel bus switch optimized for 3.3 V to 1.8 V level shifting in high-speed digital interconnects. It features two independent active-low output enables (1OE, 2OE), 5 Ω typical ON-state resistance, 600 MHz bandwidth, and rail-to-rail switching across 24-pin DHVQFN package. Used in DDR memory interface buffering and mixed-voltage FPGA I/O bridging.

For engineers reviewing the 74CBTLVD3384BQ,118 datasheet, 74CBTLVD3384BQ,118 pinout, 74CBTLVD3384BQ,118 application, or 74CBTLVD3384BQ,118 equivalent, key selection criteria include IOFF-enabled partial power-down capability, Schmitt-trigger control inputs for slow-edge tolerance, -40 °C to +125 °C operation, and verified 3.3 V ↔ 1.8 V bidirectional level translation with <0.22 ns propagation delay.

Technical Context

This device implements two independent 5-pole single-throw analog switches, each controlled by a dedicated active-low enable input (1OE/2OE). Switching occurs between A-port (1A1–1A5, 2A1–2A5) and B-port (1B1–1B5, 2B1–2B5) terminals with no internal logic inversion.

It uses CMOS transmission-gate architecture with IOFF circuitry enabling safe operation during partial power-down (VCC = 0 V), and Schmitt-trigger inputs ensure robust noise immunity for control signals up to 3.6 V regardless of supply voltage. Pass voltage remains ≤1.85 V at 4 mA load across full temperature range.

Key Specifications

Pinout & Package

DHVQFN24 (SOT815-1) package: 3.5 × 5.5 × 0.85 mm body, 24-terminal no-lead thermal-enhanced quad flat layout with exposed thermal pad (non-soldered or GND-connected per datasheet guidance).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar bus switch applications.

Compared with SN74CBT3384CPWR and 74LVC1G3157GW,125, the 74CBTLVD3384BQ,118 uniquely combines dual independent 5-bit banks, IOFF safety, –40 °C to +125 °C qualification, and 3.7 Ω RON in a space-efficient DHVQFN24 - making it optimal for thermally constrained, multi-rail embedded systems requiring deterministic level translation.

Availability

74CBTLVD3384BQ,118 is available at Aetrix Electronics and suitable for DDR memory subsystems, FPGA configuration interfaces, PCIe Gen1 multiplexing, and industrial sensor hub designs requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74CBTLVD3384BQ,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors including logic, discrete, and MOSFET devices - headquartered in Nijmegen, Netherlands, with manufacturing in Europe and Asia.

The CBTLVD series targets high-speed digital interconnect applications requiring precise level translation, low latency, and robustness in mixed-voltage systems - designed specifically for DDR, PCIe, and FPGA I/O bridging in industrial and networking equipment.

FAQ

Can 74CBTLVD3384BQ,118 operate with VCC = 2.5 V?

No. The device is specified only for 3.0 V to 3.6 V supply per Table 5. Operation outside this range violates recommended conditions and may cause undefined switching behavior, increased RON, or failure to meet 3.3 V ↔ 1.8 V level-shift accuracy. Do not use at 2.5 V.

Is the thermal pad on the DHVQFN24 package required to be soldered to ground?

No. Per datasheet section 5.1, terminal 1 (thermal pad) has no electrical or mechanical requirement to be soldered. If connected, it must remain floating or tied to GND - never left unconnected and ungrounded, as that risks ESD susceptibility and thermal impedance mismatch.

Does 74CBTLVD3384BQ,118 support hot insertion?

Yes, under defined conditions: IOFF circuitry ensures high-Z isolation when VCC = 0 V, and overvoltage-tolerant control inputs accept up to 3.6 V regardless of supply state. However, hot insertion requires strict sequencing - apply VCC before asserting nOE - and proper board-level ESD protection per IEC 61000-4-2.

What is the maximum capacitive load this switch can drive while maintaining 0.22 ns propagation delay?

The 0.22 ns max tpd is characterized with 30 pF load (Table 10). Driving >30 pF increases RC delay proportionally; at 50 pF, measured tpd rises to ~0.35 ns. For guaranteed spec compliance, keep total trace + load capacitance ≤30 pF per channel.