Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

onsemi 74FST3345DT

Name: 74FST3345DT
Brand: onsemi
SKU: 74FST3345DT
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74FST3345DT

Manufacturer:: onsemi

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: -

Datasheet:: 74FST3345DT.pdf

Description:: BUS DRIVER

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:26,075

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74FST3345DT from ON Semiconductor is an 8-bit CMOS bus switch with TTL/CMOS-compatible control inputs, 4 Ω typical on-resistance, sub-0.25 ns max propagation delay, and operation across 4.0–5.5 V supply. It enables bidirectional signal routing in high-speed memory and data bus isolation applications.

For engineers reviewing the 74FST3345DT datasheet, pinout, applications, or equivalent options, key selection criteria include low R_ON, near-zero ground bounce, dual OE control, Pb-free TSSOP-20 packaging, and compatibility with QS3345/FST3345/CBT3345 families.

Technical Context

The 74FST3345DT implements a dual-enable 8-bit analog bus switch architecture using advanced CMOS process technology. Each A-B path operates bidirectionally with no inherent directionality, and both OE1 and OE2 must be asserted low to enable conduction.

It delivers rail-to-rail switching capability with output voltage range of 0 to V_CC, supports 50 pF load capacitance per channel, and exhibits <1.0 µA standby current at 5.5 V - enabling low-noise, low-power signal gating in mixed-signal systems.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	4.0–5.5 V - compatible with standard 5 V logic rails and tolerant of supply droop during transient loading
R_ON (Typ)	4 Ω - ensures minimal voltage drop (<256 mV at 64 mA) and preserves signal integrity in high-current bus paths
t_PHL/t_PLH Max	0.25 ns - adds negligible delay in timing-critical data paths such as CPU-to-cache or FPGA I/O expansion
I_OFF Leakage	≤1.0 µA - prevents unintended current paths when disabled, critical for power-gated subsystems
Input Compatibility	TTL/CMOS - accepts 0.8 V_IL/2.0 V_IH thresholds, eliminating level-shifter requirements in legacy 5 V systems
ESD Rating	2000 V HBM - provides robust handling margin during board assembly and system integration
Operating Temp	−40°C to +85°C - qualified for industrial-grade embedded and communications equipment environments

Pinout & Package

TSSOP-20 package (Case 948E), 6.4 mm × 4.4 mm footprint, 0.65 mm pitch, Pb-free, moisture sensitivity level 1.

Pin/Terminal	Circuit Role	Design Meaning
1, 20	OE1, OE2	Dual independent enable inputs - both must be logic LOW to activate all eight A↔B channels
2–9	A0–A7	Bus A side terminals - bidirectional I/O pins connected to source-side logic (e.g., microcontroller or ASIC)
11–18	B0–B7	Bus B side terminals - bidirectional I/O pins connected to destination-side logic (e.g., memory or peripheral)
10	GND	Ground reference - single ground pin shared by all switches; requires low-inductance PCB connection
19	V_CC	Power supply - decoupling capacitor (0.1 µF ceramic) required within 5 mm for noise suppression

Key Features

Feature	Design Value
Ultra-low R_ON	4 Ω typical ensures <256 mV drop at full 64 mA per channel - preserves voltage margins in 5 V logic systems
No propagation delay	0.25 ns max - eliminates timing skew between parallel data lines, critical for synchronous bus architectures
No ground bounce	Zero switching-induced ground disturbance - prevents false triggering in adjacent sensitive analog or clock circuits
Dual OE control	Independent OE1/OE2 allows selective activation of two 4-bit subsets or redundant enable signaling for safety-critical gating
Pb-free TSSOP-20	RoHS-compliant, industry-standard 0.65 mm pitch package - supports automated SMT assembly and thermal reflow profiles

Applications

Memory Bus Isolation	CPU-to-Peripheral Interface
Use Scenario: Isolating DRAM address/data buses during power-down sequencing to prevent back-driving and leakage. IC Role / Device Role / Timing Role: Bidirectional analog switch enabling/disabling signal flow between memory controller and SDRAM banks. Use Value: Prevents current leakage and bus contention during low-power states while maintaining <0.25 ns timing alignment across all 8 bits.	Use Scenario: Gating communication between microcontroller GPIO and external ADC/DAC without adding latency. IC Role / Device Role / Timing Role: Low-R_ON signal path selector that preserves signal rise/fall times and avoids added jitter. Use Value: Enables clean hot-swap capability and dynamic peripheral enable/disable with no timing penalty or ground noise injection.
FPGA I/O Expansion	Legacy System Bus Arbitration
Use Scenario: Extending limited FPGA I/O pins to drive multiple peripheral modules via time-multiplexed access. IC Role / Device Role / Timing Role: High-speed bus switch acting as programmable I/O multiplexer under FPGA control. Use Value: Delivers 4 Ω on-resistance and sub-0.25 ns delay - maintains signal fidelity up to 1 GHz edge rates in high-speed digital interfaces.	Use Scenario: Arbitrating shared ISA or PCI bus segments between multiple masters in industrial control backplanes. IC Role / Device Role / Timing Role: Bidirectional isolation gate controlled by bus grant logic to prevent contention. Use Value: Eliminates ground bounce and adds zero propagation delay - ensures deterministic arbitration timing and signal integrity across noisy backplane environments.

Memory Bus Isolation

CPU-to-Peripheral Interface

Use Scenario: Isolating DRAM address/data buses during power-down sequencing to prevent back-driving and leakage.

IC Role / Device Role / Timing Role: Bidirectional analog switch enabling/disabling signal flow between memory controller and SDRAM banks.

Use Value: Prevents current leakage and bus contention during low-power states while maintaining <0.25 ns timing alignment across all 8 bits.

Use Scenario: Gating communication between microcontroller GPIO and external ADC/DAC without adding latency.

IC Role / Device Role / Timing Role: Low-R_ON signal path selector that preserves signal rise/fall times and avoids added jitter.

Use Value: Enables clean hot-swap capability and dynamic peripheral enable/disable with no timing penalty or ground noise injection.

FPGA I/O Expansion

Legacy System Bus Arbitration

Use Scenario: Extending limited FPGA I/O pins to drive multiple peripheral modules via time-multiplexed access.

IC Role / Device Role / Timing Role: High-speed bus switch acting as programmable I/O multiplexer under FPGA control.

Use Value: Delivers 4 Ω on-resistance and sub-0.25 ns delay - maintains signal fidelity up to 1 GHz edge rates in high-speed digital interfaces.

Use Scenario: Arbitrating shared ISA or PCI bus segments between multiple masters in industrial control backplanes.

IC Role / Device Role / Timing Role: Bidirectional isolation gate controlled by bus grant logic to prevent contention.

Use Value: Eliminates ground bounce and adds zero propagation delay - ensures deterministic arbitration timing and signal integrity across noisy backplane environments.

Equivalent & Alternatives

The following parts are listed as comparable options for similar bus switch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74FST3345DW	SOIC-20 package (751D), same electrical specs, 96 °C/W θ_JA vs. 128 °C/W for DT	Preferred for through-hole prototyping or higher thermal mass PCBs; not suitable for fine-pitch SMT lines	Select when thermal derating margin >20% is required or SOIC footprint already exists in design
SN74CBT3345CPWR	Texas Instruments part; 5 Ω R_ON, 0.25 ns delay, identical pinout but different marking and JEDEC compliance	Qualified for automotive AEC-Q100 Grade 2; wider temp range (−40°C to +125°C)	Choose for extended temperature or automotive applications where TI qualification is mandated

Compared with 74FST3345DW and SN74CBT3345CPWR, the 74FST3345DT offers optimal balance of ultra-low R_ON, minimal delay, and Pb-free TSSOP packaging for high-density industrial PCBs - while maintaining full functional equivalence with the FST3345 family.

Availability

74FST3345DT is available at Aetrix Electronics and suitable for memory bus isolation, FPGA I/O expansion, and CPU-to-peripheral interface applications requiring stable component supply, RoHS compliance, and industrial temperature support.

Supply support for 74FST3345DT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

ON Semiconductor is a global semiconductor manufacturer specializing in energy-efficient power, analog, sensor, and logic solutions for automotive, industrial, cloud, and consumer markets.

The 74FST3345DT belongs to the FST (Fast Switching Transistor) logic family - designed specifically for high-speed, low-noise bus switching in 5 V systems where timing precision and signal integrity are critical.

FAQ

What is the maximum operating voltage for the 74FST3345DT?

The 74FST3345DT supports a DC supply voltage range of 4.0 V to 5.5 V. Operation above 5.5 V violates absolute maximum ratings and may cause permanent damage. The device is optimized for 5 V systems and retains full functionality down to 4.0 V, accommodating brown-out conditions in industrial power supplies.

Does the 74FST3345DT require pull-up or pull-down resistors on its OE pins?

Yes - unused OE pins on the 74FST3345DT must not be left floating. Per datasheet Note 5, all control inputs must be tied to a defined logic level (V_CC or GND). Leaving OE1 or OE2 unconnected risks metastability, increased ICC, or unintended channel activation due to noise coupling.

Can the 74FST3345DT be used for analog signal switching?

The 74FST3345DT supports bidirectional analog signal routing within its specified voltage range (0 V to V_CC). Its 4 Ω R_ON and low charge injection make it suitable for low-frequency analog signals (e.g., audio, sensor outputs), but it is not characterized for RF or high-precision instrumentation use beyond 5 V logic-level applications.

What is the thermal resistance (θ_JA) of the 74FST3345DT in its TSSOP-20 package?

The 74FST3345DT in TSSOP-20 (Case 948E) has a junction-to-ambient thermal resistance (θ_JA) of 128 °C/W, measured per JEDEC JESD51-2 with minimum pad spacing on FR4. This value assumes standard 2-ounce copper traces and no forced airflow - actual performance improves with enhanced PCB copper area or thermal vias.

Is the 74FST3345DT pin-compatible with the CBT3345 series?

Yes - the 74FST3345DT is explicitly stated as pin-for-pin compatible with QS3345, FST3345, and CBT3345 devices. All share identical 20-pin TSSOP/SOIC/QSOP footprints, pin assignments, and truth table behavior, enabling direct substitution in existing designs without layout changes.

74FST3345DT Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: *

Package/Case:: -

Packaging:: Bulk

Product Status:: Active

Logic Type:: -

Number of Elements:: -

Number of Bits per Element:: -

Input Type:: -

Output Type:: -

Current - Output High, Low:: -

Voltage - Supply:: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

74FST3345DT FAQ

1.How can I place an order for 74FST3345DT through Aetrix?

Please submit a Request for Quotation (RFQ) for 74FST3345DT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74FST3345DT reliable?

The price and inventory of 74FST3345DT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74FST3345DT is usually 5 days.

3.What payment methods are accepted for 74FST3345DT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74FST3345DT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74FST3345DT?

74FST3345DT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74FST3345DT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74FST3345DT?

For technical support, including 74FST3345DT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74FST3345DT requirements.

6.How does Aetrix verify that 74FST3345DT is sourced from the original manufacturer or authorized distributors?

All 74FST3345DT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74FST3345DT meets industry standards.

7.What is the process for return or replacement of 74FST3345DT?

All 74FST3345DT units undergo pre-shipment inspection (PSI). If there is an issue with 74FST3345DT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74FST3345DT part is unused and in its original packaging.

Return procedure for 74FST3345DT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…