onsemi 74HC04DR2G
- Part No.:
- 74HC04DR2G
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74HC04DR2G.pdf
- Description:
- IC INVERTER 6CH 1-INP 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,331
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Product details
Overview
74HC04DR2G from onsemi is a high-performance silicon-gate CMOS hex inverter with six independent three-stage inverters, operating from 2.0 V to 6.0 V, delivering 10 LSTTL load drive capability and propagation delay as low as 13 ns at 6.0 V, used for digital signal inversion in logic interface and level-shifting circuits.
For engineers reviewing the 74HC04DR2G datasheet, pinout, applications, or equivalent options, key selection considerations include supply voltage range (2.0–6.0 V), output drive strength (±5.2 mA at 6.0 V), input compatibility with TTL/CMOS, thermal derating in SOIC-14, and Pb-free SOIC-14 packaging per JEDEC 7A.
Technical Context
The 74HC04DR2G implements six identical CMOS inverter stages using three-stage transistor-level design to achieve balanced rise/fall times and high noise immunity. Each inverter supports rail-to-rail input and output swing with guaranteed VOH ≥ 5.9 V and VOL ≤ 0.1 V at VCC = 6.0 V and IOUT = ±20 µA.
It operates across –55 °C to +125 °C, meets JEDEC Std. 7A, and features ESD protection of 2000 V HBM. Input leakage remains ≤ ±1.0 µA at 6.0 V, and quiescent ICC is ≤ 40 µA over temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - Enables direct interface with 3.3 V and 5 V logic systems without level shifters. |
| Propagation Delay (tPLH/tPHL) | 13 ns max at VCC = 6.0 V, CL = 50 pF - Supports >30 MHz toggle rates in clean digital paths. |
| Output Drive Current | ±5.2 mA at VCC = 6.0 V - Drives 10 LSTTL loads or multiple CMOS inputs without buffering. |
| Input Thresholds (VIH/VIL) | VIH = 4.20 V, VIL = 1.80 V at VCC = 6.0 V - Ensures robust noise margin (>2.0 V) in noisy industrial environments. |
| Quiescent Supply Current | ≤ 40 µA at TA = 125 °C - Enables use in low-power always-on monitoring nodes. |
| ESD Rating | HBM 2000 V - Meets IEC 61000-4-2 Level 2 for handling without special ESD controls. |
Pinout & Package
74HC04DR2G is supplied in a Pb-free SOIC-14 package (Case 751A), 8.55 mm × 3.80 mm × 1.75 mm body, with standard 1.27 mm pitch and gull-wing leads. Pin 1 is marked by a beveled corner or notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 3, 5, 9, 11, 13 | Inverter Input (A1–A6) | CMOS-compatible high-impedance inputs; require external pull-up for TTL interfacing. |
| 2, 4, 6, 8, 10, 12 | Inverter Output (Y1–Y6) | Push-pull CMOS outputs capable of sourcing/sinking up to ±5.2 mA at 6.0 V. |
| 7 | GND | Ground reference for all inputs, outputs, and internal circuitry; must be low-impedance. |
| 14 | VCC | Positive supply rail; bypassing with 0.1 µF ceramic capacitor near pin is mandatory for stable operation. |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail output swing | VOH ≥ 5.9 V / VOL ≤ 0.1 V at VCC = 6.0 V - Eliminates need for external pull-ups in open-drain configurations. |
| Three-stage inverter architecture | Optimizes propagation delay vs. power trade-off - achieves 13 ns delay with <20 µA static current at 25 °C. |
| High noise immunity | Typical noise margin >2.0 V at 6.0 V - Resists coupling from adjacent switching signals in dense PCB layouts. |
| Pb-free SOIC-14 packaging | RoHS-compliant, JEDEC-standard footprint - enables drop-in replacement of legacy 74LS04 in reflow-soldered assemblies. |
Applications
| Industrial Control Logic | Digital Sensor Interface |
|---|---|
Use Scenario: Inverting enable signals for PLC I/O modules where active-low control lines drive optocouplers or relay drivers. IC Role / Device Role / Timing Role: Signal polarity conversion with deterministic 13 ns delay to synchronize with 20 MHz system clock edges. Use Value: Eliminates discrete transistor inverters, reducing BOM count and layout area while maintaining timing predictability. | Use Scenario: Conditioning open-collector outputs from temperature or motion sensors before feeding into microcontroller GPIOs. IC Role / Device Role / Timing Role: Level-shifting and inversion of 5 V sensor signals to 3.3 V–compatible logic levels with no added jitter. Use Value: Provides clean, fast edge transitions (<19 ns transition time) critical for accurate pulse-width measurement in sensor firmware. |
| Legacy System Emulation | Power Sequencing Control |
Use Scenario: Replacing obsolete 74LS04 in retro-computing restoration projects requiring identical pinout and TTL-compatible drive. IC Role / Device Role / Timing Role: Pin-identical functional replacement with lower power and wider voltage tolerance than LS family. Use Value: Enables modern 2.0–6.0 V supply rails while preserving original board layout and timing behavior. | Use Scenario: Generating inverted reset or enable signals for multi-rail DC/DC converters during cold-start sequencing. IC Role / Device Role / Timing Role: Glitch-free inversion of power-good signals with guaranteed setup/hold margins for downstream regulators. Use Value: Prevents race conditions between 1.2 V, 3.3 V, and 5 V rails by ensuring monotonic, sub-20 ns edge alignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC04N | Dual-in-line (PDIP-14) package; same electrical specs but higher thermal resistance (θJA = 70 °C/W vs. 58 °C/W for SOIC). | Suitable for prototyping and through-hole assembly; not recommended for high-density or thermally constrained PCBs. | Select when hand-soldering or breadboarding is required; avoid for production boards exceeding 50 °C ambient. |
| MC74HC04ADTR2G | TSSOP-14 package (4.9 mm × 4.4 mm); identical AC/DC specs but 6.1 mW/°C thermal derating above 65 °C. | Better suited for space-constrained designs; requires fine-pitch reflow profile and 0.65 mm pitch stencil. | Choose for compact consumer electronics where board area is premium and thermal management includes copper pour under exposed pad. |
Compared with SN74HC04N and MC74HC04ADTR2G, the 74HC04DR2G offers optimal balance of thermal performance (58 °C/W θJA), industry-standard SOIC footprint, and Pb-free compliance-making it the preferred choice for volume industrial PCB assembly.
Availability
74HC04DR2G is available at Aetrix Electronics and suitable for industrial control logic, digital sensor interface, and legacy system emulation requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for 74HC04DR2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient innovation for automotive, industrial, cloud, and IoT applications.
The 74HC04DR2G belongs to the high-speed CMOS logic family designed specifically for reliable, low-power digital signal inversion in harsh environments and mixed-voltage systems.
FAQ
What is the maximum operating temperature for the 74HC04DR2G?
The 74HC04DR2G is rated for continuous operation from –55 °C to +125 °C across all package types. This full industrial temperature range is validated per JEDEC JESD22-A108, making the 74HC04DR2G suitable for engine control units, factory automation controllers, and outdoor telecom equipment where ambient extremes occur.
Can the 74HC04DR2G drive a 50 pF capacitive load at 10 MHz?
Yes-the 74HC04DR2G delivers 13 ns propagation delay and 13 ns output transition time (tTLH/tTHL) at VCC = 6.0 V with CL = 50 pF, supporting clean 10 MHz square-wave toggling. Its ±5.2 mA drive strength ensures minimal rise/fall time degradation even with 50 pF + 10 pF board trace capacitance, as confirmed in the AC Characteristics table on page 3 of the official datasheet.
Is the 74HC04DR2G pin-compatible with the 74LS04?
Yes-the 74HC04DR2G has identical pinout and logic function to the 74LS04, as explicitly stated in the first sentence of the datasheet: "The 74HC04 is identical in pinout to the LS04 and the MC14069." However, note that the 74HC04DR2G requires pull-up resistors for LSTTL input compatibility and operates over a wider voltage range (2.0–6.0 V vs. 4.75–5.25 V).
Does the 74HC04DR2G require external pull-up resistors on unused inputs?
Yes-unused inputs on the 74HC04DR2G must be tied to either VCC or GND to prevent floating states that cause increased ICC, oscillation, or excessive power dissipation. The datasheet's "Maximum Ratings" footnote explicitly states: "Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC)." Leaving them unconnected violates absolute maximum ratings and risks device malfunction.
What is the input capacitance of the 74HC04DR2G?
The 74HC04DR2G has a maximum input capacitance (Cin) of 10 pF per input, as specified in the AC Characteristics table on page 3 of the datasheet. This low value minimizes loading on upstream drivers and supports high-fanout configurations without degrading signal integrity-critical when driving multiple 74HC04DR2G inputs from a single microcontroller GPIO.
74HC04DR2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74HC
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Inverter
- Number of Circuits:
- 6
- Number of Inputs:
- 1
- Features:
- -
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Max):
- 2 µA
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Input Logic Level - Low:
- 0.5V ~ 1.8V
- Input Logic Level - High:
- 1.5V ~ 4.2V
- Max Propagation Delay @ V, Max CL:
- 13ns @ 6V, 50pF
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
74HC04DR2G FAQ
1.How can I place an order for 74HC04DR2G through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC04DR2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC04DR2G reliable?
The price and inventory of 74HC04DR2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC04DR2G is usually 5 days.
3.What payment methods are accepted for 74HC04DR2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC04DR2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC04DR2G?
74HC04DR2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC04DR2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC04DR2G?
For technical support, including 74HC04DR2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC04DR2G requirements.
6.How does Aetrix verify that 74HC04DR2G is sourced from the original manufacturer or authorized distributors?
All 74HC04DR2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC04DR2G meets industry standards.
7.What is the process for return or replacement of 74HC04DR2G?
All 74HC04DR2G units undergo pre-shipment inspection (PSI). If there is an issue with 74HC04DR2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC04DR2G part is unused and in its original packaging.
Return procedure for 74HC04DR2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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