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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Nexperia USA Inc. 74HC107PW,112

Name: 74HC107PW,112
Brand: Nexperia USA Inc.
SKU: 74HC107PW,112
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74HC107PW,112

Manufacturer:: Nexperia USA Inc.

Category:: Flip Flops

Package:: 14-TSSOP (0.173", 4.40mm Width)

Datasheet:: 74HC107PW,112.pdf

Description:: IC FF JK TYPE DUAL 1BIT 14TSSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74HC107PW,112 from Nexperia is a dual negative-edge-triggered JK flip-flop with asynchronous active-LOW reset, 14-pin TSSOP package, 2.0–6.0 V supply range, and guaranteed operation from –40 °C to +125 °C. It implements two independent synchronous storage elements used in digital state machines, counters, and clock-domain synchronization circuits.

For engineers reviewing the 74HC107PW,112 datasheet, 74HC107PW,112 pinout, 74HC107PW,112 application, or 74HC107PW,112 equivalent, this page delivers verified functional behavior, timing constraints (e.g., 19 ns t_pd at 4.5 V), pin-level circuit roles, real-world use cases in industrial control and serial data latching, and validated alternative parts with documented electrical and application differences.

Technical Context

This device integrates two independent JK flip-flops sharing no internal logic-each has dedicated J, K, CP, R, Q, and Q̅ terminals. The asynchronous reset overrides clock and input states, forcing Q = LOW and Q̅ = HIGH regardless of CP edge or J/K values. Operation requires J/K inputs stable for ≥20 ns before the HIGH-to-LOW clock transition (t_su = 20 ns at V_CC = 4.5 V).

It uses standard CMOS input thresholds (V_IH = 3.15 V min at V_CC = 4.5 V) and delivers rail-to-rail output swing (V_OH ≥ 3.98 V, V_OL ≤ 0.26 V at I_O = ±4 mA). Input clamp diodes allow safe interfacing to voltages exceeding V_CC, enabling mixed-voltage signal conditioning without external protection.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Type	Dual negative-edge-triggered JK flip-flop with asynchronous reset
Supply Voltage Range	2.0 V to 6.0 V - supports battery-powered, 3.3 V, and 5 V systems without level shifters
Propagation Delay (t_pd)	19 ns typical at V_CC = 4.5 V, CL = 50 pF - enables reliable operation up to 24 MHz in synchronous logic
Operating Temperature	–40 °C to +125 °C - qualified for under-hood automotive modules and industrial PLCs
Input Compatibility	CMOS-level inputs (74HC variant) - compatible with HC/HCT/TTL outputs via appropriate V_CC selection
Power Dissipation	4.0 μA typical ICC at V_CC = 6.0 V - ultra-low static current for always-on control logic

Pinout & Package

TSSOP14 plastic thin shrink small outline package (SOT402-1); 14 leads; body width 4.4 mm; 0.65 mm pitch; exposed pad not present; RoHS-compliant.

Pin/Terminal	Circuit Role	Design Meaning
1, 8	J input (sync)	Synchronous data enable: HIGH sets Q on next clock edge if K = LOW
2, 6	Q̅ output (complement)	Inverted stored state - drives complementary logic or differential bus lines
3, 5	Q output (true)	Primary stored state output - connects directly to next-stage logic or status indicators
4, 11	K input (sync)	Synchronous data disable: HIGH resets Q on next clock edge if J = LOW
9, 12	CP input (clock)	Negative-edge-triggered sampling point - only responds to HIGH-to-LOW transitions
10, 13	R input (reset)	Asynchronous active-LOW override - forces Q = LOW, Q̅ = HIGH immediately, independent of CP
7	GND	Reference ground plane - must be low-impedance connection to minimize switching noise coupling
14	V_CC	Positive supply rail - decoupling capacitor (100 nF) required within 5 mm of pin for stable operation

Key Features

Feature	Design Value
Wide supply range	2.0 V to 6.0 V - eliminates need for separate voltage regulators in multi-rail systems
High noise immunity	Typical V_NIH = 1.35 V, V_NIL = 0.8 V at V_CC = 4.5 V - rejects EMI-induced glitches on control lines
Latch-up immunity	>100 mA per JESD78 Class II Level B - prevents destructive parasitic thyristor activation during transient overvoltage
ESD robustness	HBM >2000 V, CDM >1000 V - withstands handling and board assembly without special ESD controls
Input clamp diodes	Integrated anode/cathode clamps - permit direct connection to 12 V sensors or legacy 5 V buses using series current-limiting resistors

Applications

Industrial Sequence Controller

Serial-to-Parallel Data Latch

Use Scenario: A programmable logic controller (PLC) uses discrete outputs to drive solenoid valves in timed sequence.

IC Role / Device Role / Timing Role: Each 74HC107PW,112 flip-flop stores one valve's ON/OFF state; clocked by a 1 Hz timing pulse; reset synchronizes all valves to OFF at system startup.

Use Value: Enables deterministic, glitch-free state transitions across 14+ I/O points using minimal PCB area and zero external timing components.

Use Scenario: An MCU transmits 8-bit sensor data serially over UART; a peripheral needs parallel access for ADC sampling.

IC Role / Device Role / Timing Role: Two 74HC107PW,112 devices form a 4-bit latch pair; clocked by the final bit's stop edge to capture full byte; reset clears stale data before new transmission.

Use Value: Eliminates need for dedicated shift-register ICs or FPGA resources while maintaining sub-microsecond setup/hold margins.

Digital Test Equipment Trigger Logic

Legacy Bus Interface Synchronizer

Use Scenario: A logic analyzer captures signal edges but requires precise trigger window alignment relative to system clock.

IC Role / Device Role / Timing Role: One flip-flop samples asynchronous trigger request; second stages it into main clock domain using negative-edge sampling to avoid metastability.

Use Value: Achieves <10 ns jitter in synchronized trigger assertion without requiring dual-clock FIFOs or custom ASIC logic.

Use Scenario: A modern ARM microcontroller interfaces with a legacy ISA bus operating at 8 MHz with non-aligned strobes.

IC Role / Device Role / Timing Role: Flip-flops capture ISA address/data on falling edge of IOR# or IOW#; reset clears latched values after each transaction completes.

Use Value: Provides cycle-accurate, electrically isolated handshaking between 100+ MHz SoC and 8 MHz bus without timing closure issues.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual JK flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74HCT107PW,112	TTL-compatible inputs (V_IH = 2.0 V min); identical pinout and timing	Better interoperability with legacy 5 V TTL logic; slightly higher ICC at V_CC = 5.5 V	Select when interfacing directly to 74LS/74F families without level translation
SN74HC109PWR	Positive-edge-triggered; set/reset are synchronous; different pin mapping (SO-16)	Requires PCB redesign; unsuitable for negative-edge clock domains or asynchronous reset requirements	Only consider if system clock architecture mandates rising-edge sampling and synchronous control

Compared with 74HC107PW,112, the 74HCT107PW,112 offers plug-in compatibility with TTL sources but sacrifices some noise margin, while the SN74HC109PWR changes fundamental timing behavior and cannot replace asynchronous reset functionality without logic re-architecting.

Availability

74HC107PW,112 is available at Aetrix Electronics and suitable for industrial automation controllers, test equipment trigger subsystems, serial interface bridges, and legacy bus adapters requiring stable component supply across extended temperature ranges.

Supply support for 74HC107PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74HC107 belongs to Nexperia's industry-standard 74HC logic family, designed for drop-in replacement of legacy TTL and earlier CMOS logic in space-constrained, thermally demanding applications where low power and wide voltage tolerance are critical.

FAQ

Can 74HC107PW,112 operate reliably at 2.0 V supply?

Yes. The datasheet guarantees full functionality-including t_pd ≤ 160 ns, t_su ≤ 125 ns, and V_IH ≥ 1.5 V-at V_CC = 2.0 V across –40 °C to +125 °C. This makes it suitable for coin-cell-powered IoT nodes and energy-harvesting systems where supply voltage sags below 2.5 V.

What is the maximum clock frequency supported?

At V_CC = 4.5 V and CL = 50 pF, f_max = 24 MHz (typical). At V_CC = 6.0 V, it reaches 28 MHz. These values assume clean clock edges with ≤20 ns rise/fall time and proper load capacitance-exceeding them risks metastability or skipped edges.

Does the reset input require debouncing?

No. The asynchronous reset is purely level-sensitive and immune to bounce because it asserts immediately on LOW and releases on HIGH-no internal sampling or edge detection occurs. However, long reset pulses (>100 ns) are recommended to ensure full internal node discharge across process corners.

How does input clamping affect interfacing with 12 V sensors?

Clamp diodes allow safe connection to 12 V signals when a series current-limiting resistor ≥5.6 kΩ is used (per I_IK ≤ ±20 mA limit). This avoids external Schottky diodes or voltage dividers, simplifying design for industrial analog front-ends while preserving noise immunity.

74HC107PW,112 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74HC

Package/Case:: 14-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Obsolete

Function:: Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 85 MHz

Max Propagation Delay @ V, Max CL:: 27ns @ 6V, 50pF

Trigger Type:: Negative Edge

Current - Output High, Low:: 5.2mA, 5.2mA

Voltage - Supply:: 2V ~ 6V

Current - Quiescent (Iq):: 4 µA

Input Capacitance:: 3.5 pF

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-TSSOP

74HC107PW,112 FAQ

1.How can I place an order for 74HC107PW,112 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74HC107PW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74HC107PW,112 reliable?

The price and inventory of 74HC107PW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC107PW,112 is usually 5 days.

3.What payment methods are accepted for 74HC107PW,112?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC107PW,112 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74HC107PW,112?

74HC107PW,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74HC107PW,112 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74HC107PW,112?

For technical support, including 74HC107PW,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC107PW,112 requirements.

6.How does Aetrix verify that 74HC107PW,112 is sourced from the original manufacturer or authorized distributors?

All 74HC107PW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC107PW,112 meets industry standards.

7.What is the process for return or replacement of 74HC107PW,112?

All 74HC107PW,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC107PW,112, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74HC107PW,112 part is unused and in its original packaging.

Return procedure for 74HC107PW,112:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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