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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Nexperia USA Inc. 74HC109DB,118

Name: 74HC109DB,118
Brand: Nexperia USA Inc.
SKU: 74HC109DB,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74HC109DB,118

Manufacturer:: Nexperia USA Inc.

Category:: Flip Flops

Package:: 16-SSOP (0.209", 5.30mm Width)

Datasheet:: 74HC109DB,118.pdf

Description:: IC FF JK TYPE DUAL 1BIT 16SSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

74HC109DB,118 from Nexperia is a dual positive-edge-triggered JK flip-flop with asynchronous set (active LOW) and reset (active LOW), 16-pin SO16 package, V_CC range 2.0–6.0 V, t_pd = 14–30 ns at V_CC = 6.0 V, and operation up to 81 MHz - used in synchronous logic control, state machine sequencing, and clock-domain synchronization in industrial PLCs and instrumentation.

For engineers reviewing the 74HC109DB,118 datasheet, 74HC109DB,118 pinout, 74HC109DB,118 application, or 74HC109DB,118 equivalent, this device delivers deterministic edge-triggered state storage with TTL-compatible input thresholds (via 74HCT variant), Schmitt-trigger clock input tolerance, and robust ESD protection - critical for noise-prone embedded control and digital interface design.

Technical Context

The 74HC109DB,118 implements two independent JK flip-flops sharing no internal coupling, each with dedicated J, K, CP, SD, RD, Q, and Q̅ terminals. Its positive-edge-triggered clock accepts slow-rising signals due to integrated Schmitt-trigger action on CP inputs, enabling reliable operation with non-ideal clock waveforms.

All asynchronous controls (SD, RD) override clocked behavior and operate independently per flip-flop; setup time (t_su) is 5–18 ns and hold time (t_h) is 0–5 ns depending on V_CC, ensuring predictable state transitions under defined timing margins.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	2.0 V to 6.0 V - supports mixed-voltage system interfacing and battery-powered 3.3 V/5 V logic domains.
Propagation Delay (t_pd)	14 ns (min) to 30 ns (max) at V_CC = 6.0 V - enables reliable 35 MHz synchronous operation in high-speed control loops.
Max Clock Frequency (f_max)	81 MHz at V_CC = 6.0 V - suitable for fast state sequencing in digital signal routing and counter applications.
Input Thresholds	CMOS-level (V_IH = 4.2 V, V_IL = 1.8 V @ V_CC = 6.0 V) - ensures clean logic discrimination across full supply range.
ESD Protection	HBM > 2000 V, CDM > 1000 V - provides robust handling during PCB assembly and field deployment in industrial environments.
Operating Temperature	-40 °C to +125 °C - qualified for extended-temperature industrial and automotive under-hood auxiliary logic.
Power Dissipation (P_tot)	500 mW (SO16), derating 12.4 mW/K above 110 °C - supports continuous operation in thermally constrained enclosures.

Pinout & Package

74HC109DB,118 is housed in a plastic small outline package (SO16), SOT109-1, with 16 leads, 3.9 mm body width, and standard 1.27 mm lead pitch - compatible with automated SMT placement and reflow profiles per JEDEC MS-012.

Pin/Terminal	Circuit Role	Design Meaning
1RD, 15RD	Asynchronous reset (active LOW)	Forces Q = 0, Q̅ = 1 regardless of clock or J/K state - essential for power-on initialization and fault recovery.
1SD, 11SD	Asynchronous set (active LOW)	Forces Q = 1, Q̅ = 0 independent of clock - used for known-state startup and emergency latch assertion.
1CP, 12CP	Clock input (LOW-to-HIGH edge)	Schmitt-triggered input tolerates slow edges; only transition triggers state update - eliminates metastability from noisy clocks.
1J, 2J	Synchronous data input (J)	When CP rises, J determines next Q state if K = 0 (set), or toggles if K = 1 - enables D-type emulation via J=K connection.
1K, 13K	Synchronous data input (K)	Complements J: defines reset (K=1,J=0), hold (K=0,J=0), toggle (K=1,J=1) - provides full combinational state control per cycle.
1Q, 6Q / 2Q, 10Q	True output	Active HIGH registered output reflecting current flip-flop state - drives downstream logic, LEDs, or bus lines directly.
1Q̅, 7Q̅ / 2Q̅, 9Q̅	Complement output	Active LOW mirror of Q - eliminates need for external inverters in differential signaling or enable/disable logic.
GND (8), V_CC (16)	Power terminals	Single-supply operation; decoupling capacitor required at V_CC pin to suppress switching noise and ensure stable timing.

Key Features

Feature	Design Value
Dual independent JK flip-flops	Enables compact implementation of two-bit registers or separate control channels without inter-stage coupling.
J/K inputs support D-type mode	Connecting J to K allows use as edge-triggered D flip-flop - simplifies migration from legacy DFF designs.
Schmitt-trigger clock input	Eliminates need for external RC filtering on CP lines - reduces BOM count and board space in noisy industrial settings.
Clamp diodes on all inputs	Permits safe interfacing to voltages exceeding V_CC using series current-limiting resistors - protects against overvoltage transients.
Wide temperature qualification	Specified from -40 °C to +125 °C - validated for use in motor drives, power supplies, and outdoor automation equipment.

Applications

Industrial Control Logic

Digital Signal Routing

Use Scenario: State retention in programmable logic controllers managing conveyor belt sequencing and sensor-triggered actuation cycles.

IC Role / Device Role / Timing Role: Dual JK flip-flop stores two bits of machine state (e.g., "running" and "fault active") synchronized to a 10 MHz system clock.

Use Value: Asynchronous set/reset ensures deterministic startup and emergency stop response; low propagation delay maintains tight control loop timing.

Use Scenario: Selecting between alternate data paths in FPGA I/O expansion modules with shared clock domains.

IC Role / Device Role / Timing Role: Edge-triggered register latches multiplexer select bits prior to data transfer, preventing glitches during path switching.

Use Value: Complementary Q/Q̅ outputs drive bidirectional bus drivers without added inverters; CMOS thresholds match FPGA I/O voltage levels.

Test Equipment Sequencing

Power Supply Monitoring

Use Scenario: Generating precise pulse trains and step sequences in automated test equipment for IC functional validation.

IC Role / Device Role / Timing Role: JK configuration enables toggle mode for divide-by-2 clock generation and load/set modes for pattern initialization.

Use Value: 81 MHz f_max supports high-speed test vector rates; t_rec ≤ 18 ns ensures rapid recovery after asynchronous reset during test abort.

Use Scenario: Latching overvoltage/undervoltage fault flags from analog comparators in DC-DC converter supervision circuits.

IC Role / Device Role / Timing Role: Asynchronous SD/RD inputs capture comparator alerts immediately; Q outputs feed microcontroller interrupt pins.

Use Value: Active-LOW reset aligns with open-drain comparator outputs; wide V_CC range accommodates 3.3 V supervisor rails and 5 V logic interfaces.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual JK flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74HCT109DB,118	TTL-compatible input thresholds (V_IH = 2.0 V, V_IL = 0.8 V @ V_CC = 5 V); identical pinout and timing.	Required when interfacing with legacy 5 V TTL logic families; higher input current draw vs. HC variant.	Select for mixed-logic systems with 74LS/74F components; avoid in battery-powered or low-noise CMOS-only designs.
SN74HC112DR	Same function but negative-edge-triggered clock; different pin mapping (SO16, but RD/SD on pins 1/2, CP on pin 3).	Not pin-compatible; requires PCB layout change and timing analysis for inverted clock edge alignment.	Use only when existing design uses SN74HC112 footprint; verify setup/hold timing with inverted clock polarity.

Compared with 74HCT109DB,118, the 74HC109DB,118 offers lower static current and wider V_CC flexibility but lacks TTL input compatibility; versus SN74HC112DR, it provides positive-edge triggering and direct pin compatibility but cannot substitute without schematic and layout revision.

Availability

74HC109DB,118 is available at Aetrix Electronics and suitable for industrial control logic, digital signal routing, test equipment sequencing, and power supply monitoring requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74HC109DB,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, discrete, and MOSFET solutions optimized for efficiency, miniaturization, and robustness in industrial and automotive applications.

The 74HC109DB,118 belongs to Nexperia's 74HC logic family - designed for low-power, high-noise-immunity digital control in extended-temperature environments where reliability and timing predictability are critical.

FAQ

Can 74HC109DB,118 operate at 3.3 V supply?

Yes - the 74HC109DB,118 is fully specified from 2.0 V to 6.0 V, including 3.3 V operation. At V_CC = 3.3 V, typical propagation delay is 24 ns, f_max is ~55 MHz, and input thresholds scale proportionally (V_IH ≈ 2.3 V, V_IL ≈ 1.0 V), ensuring compatibility with 3.3 V CMOS systems.

Is the SO16 package RoHS-compliant and lead-free?

Yes - the 74HC109DB,118 in SOT109-1 (SO16) package meets RoHS Directive 2011/65/EU and is lead-free, with matte tin (Sn) termination finish. It complies with JEDEC J-STD-020 moisture sensitivity level (MSL) 1, allowing unlimited floor life at ≤30 °C/60% RH.

What is the maximum capacitive load the outputs can drive?

The outputs are rated for ±25 mA DC drive capability. With CL = 50 pF (standard test condition), t_pd remains within spec up to 30 ns. For heavier loads (>100 pF), propagation delay increases linearly; output rise/fall times (t_t) remain ≤19 ns at V_CC = 6.0 V, supporting reliable driving of multiple 74HC inputs or short PCB traces.

How does the Schmitt-trigger clock input improve system reliability?

The Schmitt-trigger on CP inputs provides hysteresis (~0.3 V at V_CC = 5 V), rejecting noise below the threshold window and eliminating false triggering from slow-rising or undershoot-prone clock signals - critical in electrically noisy factory floors or long-cable clock distribution.

74HC109DB,118 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74HC

Package/Case:: 16-SSOP (0.209", 5.30mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Function:: Set(Preset) and Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 81 MHz

Max Propagation Delay @ V, Max CL:: 30ns @ 6V, 50pF

Trigger Type:: Positive Edge

Current - Output High, Low:: 5.2mA, 5.2mA

Voltage - Supply:: 2V ~ 6V

Current - Quiescent (Iq):: 4 µA

Input Capacitance:: 3.5 pF

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SSOP

74HC109DB,118 FAQ

1.How can I place an order for 74HC109DB,118 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74HC109DB,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74HC109DB,118 reliable?

The price and inventory of 74HC109DB,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC109DB,118 is usually 5 days.

3.What payment methods are accepted for 74HC109DB,118?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC109DB,118 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74HC109DB,118?

74HC109DB,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74HC109DB,118 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74HC109DB,118?

For technical support, including 74HC109DB,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC109DB,118 requirements.

6.How does Aetrix verify that 74HC109DB,118 is sourced from the original manufacturer or authorized distributors?

All 74HC109DB,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC109DB,118 meets industry standards.

7.What is the process for return or replacement of 74HC109DB,118?

All 74HC109DB,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC109DB,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74HC109DB,118 part is unused and in its original packaging.

Return procedure for 74HC109DB,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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