My Inquiry
My Account
Nexperia USA Inc. 74HC112D,653
- Part No.:
- 74HC112D,653
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Flip Flops
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74HC112D,653.pdf
- Description:
- IC FF JK TYPE DUAL 1BIT 16SO
- Quantity:
- Payment:
- Shipping:
Inventory:3,995
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HC112D,653 from Nexperia is a dual negative-edge-triggered JK flip-flop with asynchronous active-LOW set (nSD) and reset (nRD), complementary Q/nQ outputs per section, 16-pin SO16 package, and CMOS-level input compatibility. It operates from 2.0 V to 6.0 V across -40 °C to +125 °C and supports reliable state control in synchronous logic sequencers, frequency dividers, and register-based control circuits.
For engineers reviewing the 74HC112D,653 datasheet, 74HC112D,653 pinout, 74HC112D,653 application, or 74HC112D,653 equivalent, this page delivers verified functional behavior, JEDEC-compliant timing margins (e.g., 16 ns tpd at VCC = 6.0 V), SO16 mechanical data, static voltage thresholds (VIH = 4.2 V min at VCC = 6.0 V), and real-world substitution guidance for legacy 74-series logic design.
Technical Context
This device implements two independent edge-triggered JK flip-flops sharing no internal coupling-each with dedicated J, K, clock (nCP), set (nSD), reset (nRD), Q, and nQ terminals. The asynchronous nSD/nRD inputs override clocked operation and function independently of nCP transitions.
Its Schmitt-trigger clock input tolerates slow rise/fall times, while input clamp diodes allow safe interfacing to voltages exceeding VCC when used with current-limiting resistors. All inputs meet JEDEC Std. 7A, and ESD protection exceeds 2000 V HBM and 1000 V CDM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | 74HC high-speed CMOS - compatible with TTL output loads but driven by CMOS-level inputs (VIH ≥ 3.15 V at VCC = 4.5 V) |
| Supply Voltage Range | 2.0 V to 6.0 V - enables direct interface with 3.3 V and 5 V systems without level translation |
| Propagation Delay (tpd) | 16 ns max at VCC = 6.0 V, CL = 50 pF - supports >24 MHz operation in synchronous counters |
| Set/Reset Recovery Time | 14 ns min at VCC = 6.0 V - ensures stable output within one clock cycle after asynchronous assertion |
| Input Capacitance (CI) | 3.5 pF - minimizes loading on driving gates and preserves signal integrity in dense PCB layouts |
| Operating Temperature | -40 °C to +125 °C - qualified for industrial and extended-temperature embedded control applications |
| ESD Rating | HBM > 2000 V, CDM > 1000 V - reduces risk of field failure during handling and board assembly |
Pinout & Package
74HC112D,653 uses the SOT109-1 (SO16) plastic small outline package: 16-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads, and JEDEC MS-012 compliant footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 13 (1CP, 2CP) | Clock input (negative-edge triggered) | Triggers state update on HIGH-to-LOW transition; Schmitt-trigger input accepts slow edges |
| 2, 12 (1K, 2K) | JK flip-flop K input | Controls toggle/reset behavior when J = 1 and CP falls; must be stable before clock edge |
| 3, 11 (1J, 2J) | JK flip-flop J input | Controls toggle/set behavior when K = 1 and CP falls; requires setup time ≥14 ns at VCC = 6.0 V |
| 4, 10 (1SD, 2SD) | Asynchronous set (active LOW) | Forces Q = HIGH regardless of clock or J/K; overrides all other inputs when asserted |
| 5, 9 (1Q, 2Q) | True output | Complementary to nQ; drives standard CMOS/TTL loads up to ±25 mA |
| 6, 7 (1Q, 2Q) | Complement output | Inverted version of Q; eliminates need for external inverters in toggle or feedback paths |
| 8 | GND | Reference ground plane connection; decoupling capacitor placement critical for noise immunity |
| 14, 15 (1RD, 2RD) | Asynchronous reset (active LOW) | Forces Q = LOW regardless of clock or J/K; independent timing from nSD |
| 16 | VCC | Positive supply rail; requires local 100 nF ceramic decoupling adjacent to pin |
Key Features
| Feature | Design Value |
|---|---|
| Asynchronous set/reset | Independent, active-LOW nSD/nRD pins enable immediate state initialization without clock dependency |
| Schmitt-trigger clock input | Enables robust operation with RC-generated clocks or noisy system clocks having >100 ns rise/fall times |
| Input clamp diodes | Allow safe interfacing to signals up to VCC + 0.5 V using series current-limiting resistors |
| JEDEC Std. 7A compliance | Guarantees interoperability with legacy 74-series logic families and standardized test methodologies |
| Wide temperature range | Specified from -40 °C to +125 °C - suitable for under-hood automotive modules and industrial PLCs |
Applications
| Industrial Control Sequencer | Digital Frequency Divider |
|---|---|
|
Use Scenario: A programmable logic controller (PLC) uses cascaded 74HC112D,653 devices to implement a 4-bit binary counter controlling motor start/stop cycles. IC Role / Device Role / Timing Role: Each flip-flop serves as a stage in a synchronous ripple counter, toggling on every falling edge of its predecessor's Q output. Use Value: Complementary Q/nQ outputs eliminate external inverters; 16 ns propagation delay ensures clean carry propagation up to 24 MHz base clock. |
Use Scenario: A microcontroller generates a 10 MHz reference clock, which must be divided by 3 for an ADC sampling trigger. IC Role / Device Role / Timing Role: Configured in toggle mode (J=K=1), the 74HC112D,653 divides input frequency by 2 per stage; two stages yield ÷4, with NAND feedback enabling ÷3. Use Value: Asynchronous reset allows precise alignment of division phase; low ICC (≤80 μA) minimizes power in battery-backed timing subsystems. |
| Serial-to-Parallel Shift Register Stage | State Machine Controller |
|
Use Scenario: An LED display driver converts serial data from an MCU into parallel 8-bit segments using shift-and-latch architecture. IC Role / Device Role / Timing Role: One 74HC112D,653 holds the latch enable bit; another stores serial-in data before parallel transfer on rising edge of load signal. Use Value: Dual independent sections reduce component count; set/reset pins enable deterministic initialization before data capture begins. |
Use Scenario: A vending machine controller implements a 3-state finite state machine (idle, select, dispense) using combinational logic and memory. IC Role / Device Role / Timing Role: Flip-flops store current state bits; J/K inputs receive next-state logic from AND-OR gate array; clock synchronizes transitions. Use Value: Predictable setup/hold timing (tsu = 14 ns, th = 0 ns at VCC = 6.0 V) simplifies timing closure; wide VCC range accommodates mixed-voltage board design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual JK flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT112D,653 | TTL-compatible inputs (VIH = 2.0 V min); identical pinout and AC specs | Better suited for mixed 74LS/74HC systems where driving sources are legacy TTL | Select when interfacing directly to 74LS or older microcontroller GPIO without level shifters |
| SN74HC112DR | Same logic function and DC specs; SOIC-16 package (same footprint), but TI-specified thermal derating | Identical use cases; minor differences in ICC max (TI: 50 μA vs Nexperia: 80 μA at 125 °C) | Use when sourcing from TI-authorized channels or requiring TI-specific qualification documentation |
Compared with 74HCT112D,653, the 74HC112D,653 offers higher noise immunity in CMOS-driven systems, while SN74HC112DR provides equivalent functionality with alternate supply-chain assurance-neither is pin- or timing-drop-in without verifying board-level decoupling and thermal layout.
Availability
74HC112D,653 is available at Aetrix Electronics and suitable for industrial automation controllers, test equipment timing modules, and consumer electronics power sequencing circuits requiring stable component supply across extended temperature ranges and multi-year production cycles.
Supply support for 74HC112D,653 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and discrete components with rigorous quality and reliability standards.
The 74HC112D,653 belongs to Nexperia's 74HC logic family-designed for low-power, high-noise-immunity digital control in industrial, computing, and communications infrastructure where predictable timing and wide VCC tolerance are critical.
FAQ
Can 74HC112D,653 operate reliably at 3.3 V?
Yes. The 74HC112D,653 is fully specified from 2.0 V to 6.0 V, with VIH = 1.5 V min and VIL = 0.5 V max at VCC = 2.0 V, scaling linearly. At 3.3 V, VIH ≥ 2.31 V and VIL ≤ 1.09 V, ensuring robust compatibility with 3.3 V microcontrollers and FPGAs without level shifting.
What happens if both nSD and nRD go HIGH simultaneously after being LOW?
Per the function table, simultaneous LOW-to-HIGH transitions on nSD and nRD result in unpredictable output states (q/q indeterminate). To avoid metastability, assert only one asynchronous control at a time, or ensure proper sequencing via external logic or firmware delays before releasing both.
Is the SO16 package RoHS-compliant and lead-free?
Yes. The SOT109-1 package used for 74HC112D,653 is RoHS-compliant and lead-free, meeting EU Directive 2011/65/EU and JEDEC J-STD-609 Category 3 marking requirements. Nexperia confirms full compliance in its product change notifications and material declarations.
How does the Schmitt-trigger clock input improve system robustness?
The Schmitt-trigger action provides hysteresis (~0.3 V typical at VCC = 4.5 V), rejecting noise spikes and allowing reliable triggering even with slow-rising clock signals (e.g., from RC oscillators or long PCB traces), eliminating false clocking that would occur with a standard CMOS input threshold.
74HC112D,653 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Set(Preset) and Reset
- Type:
- JK Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 71 MHz
- Max Propagation Delay @ V, Max CL:
- 30ns @ 6V, 50pF
- Trigger Type:
- Negative Edge
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 3.5 pF
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
74HC112D,653 FAQ
1.How can I place an order for 74HC112D,653 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC112D,653 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC112D,653 reliable?
The price and inventory of 74HC112D,653 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC112D,653 is usually 5 days.
3.What payment methods are accepted for 74HC112D,653?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC112D,653 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC112D,653?
74HC112D,653 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC112D,653 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC112D,653?
For technical support, including 74HC112D,653 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC112D,653 requirements.
6.How does Aetrix verify that 74HC112D,653 is sourced from the original manufacturer or authorized distributors?
All 74HC112D,653 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC112D,653 meets industry standards.
7.What is the process for return or replacement of 74HC112D,653?
All 74HC112D,653 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC112D,653, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC112D,653 part is unused and in its original packaging.
Return procedure for 74HC112D,653:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HC112D,653 Tags
-
SN74HC74DR
Texas Instruments
-
SN74HC74PWR
Texas Instruments
-
74LVC1G74GT,115
Nexperia USA Inc.
-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments
-
SN74HCT273PWR
Texas Instruments
-
SN74LVC1G74DCUR
Texas Instruments
-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.
-
SN74HC273DWR
Texas Instruments
-
SN74HCT574DWR
Texas Instruments
-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…
Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…
Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.
18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…
Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…
Product Change Notification guide for electronic components, covering PCN meaning, PCN vs PDN/EOL, common change types, risk levels, form-fit-function review, engineering validation, BOM control, LTB/L…
A practical guide to blend door actuators, covering HVAC function, symptoms, location, AC and heater issues, reset and calibration, replacement cost, electrical diagnosis, compatibility checks, and rep…
Engineering guide to Raspberry Pi alternatives, covering chip-level differences, Orange Pi, ROCK, Jetson, Banana Pi, NanoPi, Compute Module, Pico, GPIO, camera, HAT compatibility, and replacement risks…
