Nexperia USA Inc. 74HC112DB,118

Overview

74HC112DB,118 from Nexperia is a dual negative-edge-triggered JK flip-flop with asynchronous active-LOW set (nSD) and reset (nRD), complementary Q/nQ outputs per section, CMOS-level input compatibility, and operation up to 71 MHz at VCC = 6.0 V. It implements discrete sequential logic in digital control circuits, clock-domain synchronization, and state-machine registers where deterministic edge-triggered behavior and independent asynchronous control are required.

For engineers reviewing the 74HC112DB,118 datasheet, 74HC112DB,118 pinout, 74HC112DB,118 application, or 74HC112DB,118 equivalent, this page delivers verified functional identity, SO16 package mapping, exact pin roles, propagation delay values across voltage/temperature ranges, static input/output thresholds, and validated alternatives for logic-level-compatible JK flip-flop replacement.

Technical Context

This device integrates two independent JK flip-flops sharing no internal coupling-each with dedicated J, K, clock (nCP), set (nSD), reset (nRD), Q, and nQ terminals. The negative-edge trigger responds only to HIGH-to-LOW transitions on nCP, while nSD and nRD override clocked operation asynchronously when asserted LOW.

Input clamping diodes enable safe interfacing to voltages exceeding VCC; Schmitt-trigger action on nCP ensures robust timing with slow-rising/falling clocks. Operation is specified from −40 °C to +125 °C, with VIH/VIL thresholds defined for both 74HC (CMOS) and 74HCT (TTL-compatible) variants-though 74HC112DB,118 specifically conforms to HC logic levels.

Key Specifications

Pinout & Package

74HC112DB,118 is supplied in the SO16 (SOT109-1) plastic small outline package: 16-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads. Pin 1 is marked by a notch or bevel; pin numbering follows standard IC convention (counterclockwise from top-left corner).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual JK flip-flop applications.

Compared with 74HC112DB,118, the 74HCT112DB,118 offers seamless integration into mixed-logic systems but sacrifices some noise margin at low VCC, while SN74LS112N imposes strict 5 V operation and higher power-making the HC variant optimal for modern low-voltage, low-power, and robust industrial use cases.

Availability

74HC112DB,118 is available at Aetrix Electronics and suitable for industrial PLCs, digital audio interfaces, legacy bus controllers, and automated test equipment requiring stable component supply, long-term lifecycle assurance, and guaranteed SO16 packaging consistency.

Supply support for 74HC112DB,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies-delivering high-performance, reliable, and scalable logic, analog, and discrete components for industrial, automotive, and consumer markets.

The 74HC112 belongs to Nexperia's 74HC logic family, engineered for low-power, high-noise-immunity digital control in space-constrained and thermally demanding environments-prioritizing robustness, wide supply range, and interoperability across voltage domains.

FAQ

What is the maximum clock frequency supported by 74HC112DB,118?

The 74HC112DB,118 achieves a maximum operating frequency of 71 MHz at VCC = 6.0 V and CL = 50 pF. At 4.5 V, it supports up to 64 MHz, and at 2.0 V, the limit drops to 20 MHz. These values assume proper load capacitance, stable supply, and adherence to setup/hold timing-verified per JEDEC-standard test conditions in the official Nexperia datasheet Rev. 5.

Can 74HC112DB,118 be used with a 3.3 V supply?

Yes-74HC112DB,118 is fully specified from 2.0 V to 6.0 V, including 3.3 V operation. At VCC = 3.3 V, VIH is guaranteed ≥2.1 V and VIL ≤1.35 V, ensuring compatibility with standard 3.3 V CMOS outputs. Propagation delay increases to ~25 ns typical, and fmax reduces to approximately 40 MHz, remaining suitable for most mid-speed control applications.

How does the asynchronous set/reset behave when both nSD and nRD go HIGH simultaneously?

If nSD and nRD transition from LOW to HIGH at the same time, the resulting output states (Q and nQ) are undefined and unpredictable per the datasheet's functional description. This race condition must be avoided in design-either by sequencing the releases (e.g., release nRD first, then nSD after ≥trec) or by ensuring only one is asserted at power-up via RC reset networks calibrated to meet trec ≥17 ns @ VCC = 6 V.

Is there a TSSOP variant of this part, and how does it differ electrically?

Yes-the 74HC112PW,118 uses the TSSOP16 (SOT403-1) package. Electrically, it is identical to the SO16 74HC112DB,118: same timing, thresholds, drive strength, and thermal specs. The only differences are mechanical-smaller footprint (4.4 mm width vs. 3.9 mm), thinner profile, and tighter lead pitch (0.65 mm)-requiring adjusted PCB land patterns and reflow profiles, but no schematic or firmware changes.