NXP Semiconductors 74HC123D/AUJ
- Part No.:
- 74HC123D/AUJ
- Manufacturer:
- NXP Semiconductors
- Category:
- Multivibrators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74HC123D/AUJ.pdf
- Description:
- IC MULTIVIBRATOR 24NS 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:3,330
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HC123D/AUJ from Nexperia is a dual retriggerable monostable multivibrator with independent reset inputs, designed for precise pulse generation and timing control in digital systems. It operates from 2.0 V to 6.0 V, delivers propagation delays as low as 19 ns (VCC = 6.0 V), supports external timing components (REXT up to 1000 kΩ, CEXT up to 100 nF), and features Schmitt-trigger inputs for noise immunity - used in debounce circuits, event stretching, and programmable delay generators.
For engineers reviewing the 74HC123D/AUJ datasheet, 74HC123D/AUJ pinout, 74HC123D/AUJ application, or 74HC123D/AUJ equivalent, key selection considerations include its dual independent monostable architecture, retriggerable pulse extension capability, direct active-low reset per channel, SO16 package compatibility, and CMOS-level input thresholds enabling interoperability with mixed-voltage logic families.
Technical Context
The 74HC123D/AUJ implements two fully independent monostable multivibrators sharing only VCC and GND. Each channel uses edge-triggered inputs (nA: negative-edge, nB: positive-edge) with Schmitt-trigger action, allowing robust operation with slow-rising signals. Pulse width is externally set via REXT and CEXT on pins nREXT/CEXT and nCEXT, with typical tW ranging from 75 ns (REXT = 5 kΩ, CEXT = 0 pF) to 450 μs (REXT = 10 kΩ, CEXT = 100 nF).
Each monostable supports real-time pulse extension via retriggering before timeout and immediate termination via LOW-going edge on dedicated nRD. Input clamping diodes permit interface to voltages exceeding VCC when current-limiting resistors are used, and latch-up immunity exceeds 100 mA per JESD78 Class II Level B.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | 2.0 V to 6.0 V - enables direct interfacing with 3.3 V and 5 V logic without level shifters. |
| Propagation delay (tpd) | 19 ns (min) at VCC = 6.0 V - ensures tight timing control in high-speed digital sequencing. |
| Pulse width range (tW) | 75 ns to 450 μs - programmable via external REXT (2–1000 kΩ) and CEXT (0–100 nF) for flexible timing design. |
| Input threshold type | CMOS-level (VIH = 4.2 V, VIL = 1.8 V at VCC = 6.0 V) - guarantees clean switching with standard HC logic drivers. |
| Operating temperature | -40 °C to +125 °C - qualified for automotive under-hood and industrial control environments. |
| Output drive strength | ±25 mA - sufficient to directly drive LEDs, small relays, or fan-out to ≥10 74HC loads. |
| Power dissipation capacitance | 54 pF per monostable - enables accurate dynamic power estimation using PD = CPD × VCC² × fi. |
Pinout & Package
74HC123D/AUJ is housed in a plastic small outline package (SO16, SOT109-1) with 16 leads, 3.9 mm body width, and standard 1.27 mm lead pitch - compatible with automated PCB assembly and legacy footprint designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A | Negative-edge trigger input (Channel 1) | Starts or extends Channel 1 output pulse on falling edge; Schmitt-triggered for noise rejection. |
| 1B | Positive-edge trigger input (Channel 1) | Starts or extends Channel 1 output pulse on rising edge; Schmitt-triggered. |
| 1RD | Direct reset input (Channel 1) | Terminates Channel 1 output pulse immediately on LOW-going edge; also accepts positive-edge trigger. |
| 1Q | Active-HIGH output (Channel 1) | Complementary to 1Q; driven HIGH during monostable timeout period. |
| 1Q | Active-LOW output (Channel 1) | Drives LOW during monostable timeout; provides inverted logic state for direct enable/disable control. |
| 1CEXT | External capacitor connection (Channel 1) | Connects timing capacitor CEXT1; must be grounded externally per datasheet recommendation to minimize noise. |
| 1REXT/CEXT | Shared resistor/capacitor node (Channel 1) | Connects timing resistor REXT1 and CEXT1; inherent pin capacitance ≈7 pF affects precision at low values. |
| GND | Ground reference (Pin 8) | Common return path for all internal circuitry and external timing components. |
| VCC | Supply voltage (Pin 16) | Primary power rail; decoupling capacitor (100 nF) recommended adjacent to this pin. |
| 2A, 2B, 2RD, 2Q, 2Q, 2CEXT, 2REXT/CEXT | Identical functions for Channel 2 | Independent duplicate of Channel 1's I/O structure - no cross-channel coupling or shared timing resources. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent monostables | Two fully isolated timing channels share only VCC/GND - enables concurrent pulse generation without interference. |
| Retriggerable operation | Output pulse can be extended indefinitely by successive triggers before timeout - ideal for event stretching or watchdog timeout extension. |
| Direct active-low reset | Asynchronous nRD input terminates output pulse within 19 ns (VCC = 6.0 V) - critical for fail-safe system recovery. |
| Schmitt-trigger inputs | Input hysteresis >0.5 V (typ.) rejects noise on slow-rising/falling signals - eliminates false triggering in noisy industrial environments. |
| Clamp diode protection | Internal input diodes allow safe interface to voltages >VCC when series current-limiting resistors are used - simplifies mixed-supply interfacing. |
Applications
| Switch Debounce | Programmable Delay Generator |
|---|---|
Use Scenario: Mechanical switch closure in industrial HMI panels generates contact bounce lasting 1–10 ms. IC Role / Device Role / Timing Role: 74HC123D/AUJ Channel 1 acts as a hardware debouncer, generating a clean, glitch-free output pulse after bounce settles. Use Value: Eliminates need for software polling or RC+Schmitt circuits; tW set to 10 ms via REXT = 100 kΩ and CEXT = 100 nF ensures reliable suppression. | Use Scenario: Microcontroller GPIO requires precise 500 μs delay between SPI chip-select assertion and data clock enable. IC Role / Device Role / Timing Role: 74HC123D/AUJ Channel 2 provides deterministic, jitter-free delay using external REXT/CEXT network. Use Value: Achieves sub-microsecond accuracy (±5%) across -40 °C to +125 °C - superior to RC-based or firmware delays. |
| Event Stretching | Watchdog Timeout Extension |
Use Scenario: A sensor interrupt occurs repeatedly every 50 ms, but system requires minimum 200 ms pulse to activate actuator. IC Role / Device Role / Timing Role: 74HC123D/AUJ Channel 1 configured in retriggerable mode extends output pulse each time sensor fires. Use Value: Output remains HIGH for full 200 ms even if interrupts stop early - prevents premature actuator deactivation. | Use Scenario: System watchdog timer must be refreshed before timeout, but processor may stall unpredictably. IC Role / Device Role / Timing Role: 74HC123D/AUJ Channel 2 generates 1 s watchdog strobe; retriggered by periodic CPU heartbeat signal. Use Value: Guarantees system reset if heartbeat stops for >1 s - independent of software execution, enhancing safety-critical reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT123D | TTL-compatible inputs (VIH = 2.0 V, VIL = 0.8 V at VCC = 5 V); identical timing, SO16 package. | Required when interfacing with legacy 5 V TTL logic families; not suitable for 3.3 V-only systems without level translation. | Select 74HCT123D only when driving from 74LS/74F sources; otherwise 74HC123D/AUJ offers wider supply range and lower input current. |
| SN74LV123ADR | Lower VCC range (2.0–5.5 V); higher speed (tpd = 11 ns typ. at VCC = 5 V); same pinout; LV logic family. | Better suited for battery-powered 3.3 V systems requiring ultra-low quiescent current (ICC = 2 μA max) and faster response. | Choose SN74LV123ADR for portable designs needing <10 μA ICC and sub-15 ns delays; 74HC123D/AUJ preferred for 6 V operation or legacy 5 V compatibility. |
Compared with 74HCT123D and SN74LV123ADR, the 74HC123D/AUJ uniquely balances wide supply voltage (2–6 V), robust noise immunity (Schmitt inputs), and proven industrial temperature qualification (-40 °C to +125 °C), making it optimal for mixed-voltage embedded control where reliability outweighs marginal speed gains.
Availability
74HC123D/AUJ is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, and consumer appliance control systems requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for 74HC123D/AUJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and discrete components with industry-leading quality and reliability.
The 74HC123D/AUJ belongs to Nexperia's 74HC logic family, engineered for low-power, high-noise-immunity digital timing applications in harsh environments - emphasizing robustness, wide operating margins, and seamless integration with microcontrollers and sensors.
FAQ
What is the maximum external timing capacitor value supported by the 74HC123D/AUJ?
The 74HC123D/AUJ supports external timing capacitors up to 100 nF, as validated in the datasheet's dynamic characteristics table (tW = 450 μs at CEXT = 100 nF, REXT = 10 kΩ). Larger values increase pulse width but reduce timing accuracy due to leakage and parasitic effects; for CEXT > 10 nF, the formula tW = K × REXT × CEXT applies, with K = 0.45 at VCC = 5.0 V.
Does the 74HC123D/AUJ require external pull-up or pull-down resistors on its trigger inputs?
No, the 74HC123D/AUJ does not require external pull-up or pull-down resistors on its 1A, 1B, 2A, or 2B inputs because they feature built-in Schmitt-trigger action with defined hysteresis. However, unused inputs must be tied to VCC or GND to prevent floating states; the datasheet explicitly recommends grounding pins 1CEXT and 2CEXT to minimize noise coupling into the timing network.
Can the 74HC123D/AUJ operate reliably at 3.3 V supply voltage?
Yes, the 74HC123D/AUJ is fully specified for operation at 3.3 V (within its 2.0 V to 6.0 V range). At VCC = 3.3 V, VIH = ~2.3 V and VIL = ~1.0 V (interpolated from datasheet curves), ensuring compatibility with 3.3 V microcontrollers and FPGAs. Propagation delay increases to ~35 ns (typ.), and output drive remains ±25 mA - sufficient for most 3.3 V logic interfacing.
How does the retrigger time (trtrig) of the 74HC123D/AUJ depend on external components?
The retrigger time trtrig of the 74HC123D/AUJ depends directly on REXT and CEXT values: for VCC = 5.0 V and CEXT > 10 pF, trtrig = 30 + 0.19 × REXT × CEXT⁰·⁹ + 13 × REXT¹·⁰⁵ (ns). This ensures the monostable only extends its output pulse when trigger edges are spaced farther apart than trtrig - preventing unintended extension from high-frequency noise or jitter.
Is the 74HC123D/AUJ pin-compatible with the 74LS123?
No, the 74HC123D/AUJ is not pin-compatible with the 74LS123. While both are dual monostables, the 74LS123 uses different pin assignments (e.g., LS123 has separate R and C pins per channel, no Schmitt inputs, and TTL thresholds). The 74HC123D/AUJ follows the industry-standard 74HC123 pinout defined in SOT109-1, which differs electrically and physically from the older 74LS123 DIP-16 layout.
74HC123D/AUJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- Yes
- Propagation Delay:
- 24 ns
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2 V ~ 6 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
74HC123D/AUJ FAQ
1.How can I place an order for 74HC123D/AUJ through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC123D/AUJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC123D/AUJ reliable?
The price and inventory of 74HC123D/AUJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC123D/AUJ is usually 5 days.
3.What payment methods are accepted for 74HC123D/AUJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC123D/AUJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC123D/AUJ?
74HC123D/AUJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC123D/AUJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC123D/AUJ?
For technical support, including 74HC123D/AUJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC123D/AUJ requirements.
6.How does Aetrix verify that 74HC123D/AUJ is sourced from the original manufacturer or authorized distributors?
All 74HC123D/AUJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC123D/AUJ meets industry standards.
7.What is the process for return or replacement of 74HC123D/AUJ?
All 74HC123D/AUJ units undergo pre-shipment inspection (PSI). If there is an issue with 74HC123D/AUJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC123D/AUJ part is unused and in its original packaging.
Return procedure for 74HC123D/AUJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HC123D/AUJ Tags

-
SN74LVC1G123DCUR
Texas Instruments
-
CD4047BM96
Texas Instruments

-
SN74LVC1G123DCTR
Texas Instruments
-
CD74HC221M96
Texas Instruments

-
CD14538BE
Texas Instruments

-
SN74LVC1G123YZPR
Texas Instruments

-
SN74LVC1G123DCUT
Texas Instruments
-
MC14538BDR2G
onsemi

-
74VHC123AMX
onsemi

-
LTC6993CS6-2#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-3#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-1#TRMPBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
