Nexperia USA Inc. 74HC123DB,112
- Part No.:
- 74HC123DB,112
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Multivibrators
- Package:
- 16-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74HC123DB,112.pdf
- Description:
- IC MULTIVIBRATOR 65NS 16SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,533
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HC123DB,112 from Nexperia is a dual retriggerable monostable multivibrator with independent reset inputs, operating across 2.0 V to 6.0 V supply. Each channel provides programmable pulse width via external REXT/CEXT, supports edge-triggered retriggering (nA/nB), and features direct LOW-going reset (nRD). It delivers 75 ns minimum pulse width (REXT = 5 kΩ, CEXT = 0 pF) and operates from –40 °C to +125 °C in SO16 package - used in timing control, debounce, and pulse extension circuits.
For engineers reviewing the 74HC123DB,112 datasheet, 74HC123DB,112 pinout, 74HC123DB,112 application, or 74HC123DB,112 equivalent, this page provides verified functional behavior, validated SO16 pin mapping, confirmed retrigger timing (110 ns min), real-world power-up/power-down mitigation guidance, and cross-referenced alternatives for industrial timing designs.
Technical Context
The device implements two independent CMOS monostable circuits, each with Schmitt-trigger inputs on nA/nB (enabling tolerance to slow edges), clamped inputs for overvoltage interface, and separate active-LOW reset (nRD) that terminates output pulses asynchronously. Pulse width is determined by external REXT/CEXT networks connected to pins 7/15 (2REXT/CEXT, 1REXT/CEXT) and 6/14 (2CEXT, 1CEXT).
Retriggering extends the output pulse period indefinitely - e.g., at VCC = 5.0 V with REXT = 5 kΩ and CEXT = 0 pF, tW ≥ 75 ns and trtrig = 110 ns - while reset propagation delay is as low as 19 ns (VCC = 6.0 V). The SO16 package (SOT109-1) supports industrial thermal range (–40 °C to +125 °C) and meets JESD78 Class II Level B latch-up immunity (>100 mA).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | 2.0 V to 6.0 V - enables direct interface with 3.3 V and 5 V logic systems without level shifters. |
| Pulse width (min) | 75 ns (REXT = 5 kΩ, CEXT = 0 pF) - supports high-speed timing windows in digital control loops. |
| Retrigger time | 110 ns (VCC = 5.0 V) - defines minimum interval between valid trigger edges to extend output pulse. |
| Propagation delay | 19 ns (VCC = 6.0 V, nRD → nQ) - ensures fast reset response critical in fault-clearing applications. |
| Operating temperature | –40 °C to +125 °C - qualified for under-hood automotive and industrial motor drive environments. |
| Input logic type | CMOS-level compatible - VIH = 3.15 V (VCC = 4.5 V), VIL = 1.35 V - matches standard HC logic families. |
| Output drive | ±4 mA (VCC = 4.5 V) - sufficient to directly drive LEDs, small MOSFET gates, or TTL inputs. |
Pinout & Package
74HC123DB,112 is supplied in SO16 plastic small outline package (SOT109-1), 16-pin, 3.9 mm body width, with gull-wing leads and pin 1 index marker. Thermal resistance θJA = 80.6 K/W (JEDEC Std 22-A104); Ptot derates linearly at 12.4 mW/K above 110 °C.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 9, 10 | nA, nB, 2A, 2B | Edge-triggered inputs: 1A/2A accept negative-edge, 1B/2B accept positive-edge triggers. |
| 3, 11 | 1RD, 2RD | Direct reset: LOW-going edge forces immediate nQ = LOW / nQ = HIGH termination. |
| 4, 12 | 1Q, 2Q | Active-LOW outputs - sink current when asserted; used for enable/disable signaling. |
| 5, 13 | 2Q, 1Q | Active-HIGH outputs - source current when asserted; complementary to 1Q/2Q. |
| 6, 14 | 2CEXT, 1CEXT | External capacitor connection points - must be grounded externally per Fig. 11 to minimize noise. |
| 7, 15 | 2REXT/CEXT, 1REXT/CEXT | Shared resistor/capacitor node - sets base pulse width; inherent pin capacitance ≈ 7 pF. |
| 8 | GND | Ground reference - all timing and logic thresholds referenced to this node. |
| 16 | VCC | Supply input - decoupling capacitor (100 nF ceramic) required within 10 mm of pin. |
Key Features
| Feature | Design Value |
|---|---|
| Retriggerable operation | Enables indefinite pulse extension - essential for watchdog timeout stretching or manual hold functions. |
| Schmitt-trigger inputs | Input hysteresis > 0.5 V (VCC = 4.5 V) - eliminates chatter on noisy switch or encoder signals. |
| Clamped input diodes | Supports interface to voltages up to VCC + 0.5 V using series current-limiting resistors. |
| Wide temperature range | –40 °C to +125 °C operation - validated for automotive engine control and industrial PLC modules. |
| Low dynamic power | CPD = 54 pF per monostable - reduces switching losses in battery-powered timing circuits. |
Applications
| Switch Debounce | Watchdog Timer Extension |
|---|---|
|
Use Scenario: Mechanical pushbutton interfacing in industrial HMI panels where contact bounce causes false interrupts. IC Role / Device Role / Timing Role: Monostable channel 1 filters bounce by generating a clean, fixed-duration LOW pulse after first edge. Use Value: Eliminates need for RC+Schmitt hardware; programmable width (via REXT/CEXT) allows tuning to specific switch characteristics. |
Use Scenario: Microcontroller watchdog timeout extension during firmware update or calibration sequences. IC Role / Device Role / Timing Role: Retriggerable monostable holds reset release signal HIGH until final software step completes. Use Value: Prevents spurious resets without modifying MCU firmware - retriggering extends pulse beyond nominal timeout window. |
| Pulse Width Modulation Gate Control | Power Sequencing Delay |
|
Use Scenario: Enabling gate drivers for synchronous buck converters requiring precise dead-time control. IC Role / Device Role / Timing Role: Generates adjustable delay between high-side and low-side FET enable signals. Use Value: External REXT/CEXT selection allows fine-tuning of dead time (75 ns to >100 μs) without layout changes. |
Use Scenario: Staged power-up of FPGA + memory subsystem where core voltage must stabilize before I/O rails. IC Role / Device Role / Timing Role: Channel 2 generates fixed delay after core rail OK signal before asserting memory enable. Use Value: Replaces discrete RC timers with guaranteed monotonic delay and temperature-stable timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT123DB,112 | TTL-compatible inputs (VIH = 2.0 V min), identical SO16 package and timing specs. | Better suited for mixed 5 V TTL/CMOS systems where input thresholds must match legacy logic. | Select when interfacing with 74LS or 74F series; otherwise 74HC123DB,112 offers wider VCC range. |
| SN74LV123ADR | Lower VCC range (2.0–5.5 V), higher drive (±6 mA), but no Schmitt inputs on A/B pins. | Lacks built-in noise immunity on trigger inputs - requires external filtering for noisy environments. | Prefer for cost-sensitive 3.3 V-only designs where external RC filtering is acceptable. |
Compared with 74HCT123DB,112 and SN74LV123ADR, the 74HC123DB,112 uniquely combines wide supply range, Schmitt-trigger noise immunity, and industrial temperature rating - making it optimal for robust timing in mixed-voltage industrial controls.
Availability
74HC123DB,112 is available at Aetrix Electronics and suitable for industrial motor drives, automotive body controllers, and medical diagnostic equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74HC123DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and discrete components - serving automotive, industrial, and consumer markets with ISO/TS 16949-certified manufacturing.
The 74HC123 belongs to Nexperia's High-Speed CMOS logic family, designed specifically for robust, low-power timing and waveform shaping in harsh-environment embedded systems.
FAQ
What is the minimum external capacitor value supported for stable pulse width generation?
The datasheet specifies stable operation down to CEXT = 0 pF (with REXT = 5 kΩ), yielding tW ≥ 75 ns. For CEXT < 50 pF, a power-up reset pulse is mandatory per Section 11.2. Practical designs use ≥100 pF to ensure monotonic timing and reduce sensitivity to parasitic capacitance.
Can both monostable channels share the same REXT/CEXT network?
No - each channel requires dedicated REXT and CEXT components. Pins 7/15 (2REXT/CEXT, 1REXT/CEXT) and 6/14 (2CEXT, 1CEXT) are electrically isolated. Shared components would cause crosstalk and unpredictable pulse widths due to internal node coupling.
How does the reset input (nRD) interact with ongoing retriggering?
An active LOW on nRD immediately terminates the output pulse regardless of retrigger activity - nQ goes LOW and nQ goes HIGH within tpd ≤ 19 ns (VCC = 6.0 V). Retrigger edges arriving during reset assertion are ignored until nRD returns HIGH.
Is the SO16 package (SOT109-1) RoHS-compliant and lead-free?
Yes - 74HC123DB,112 conforms to RoHS Directive 2011/65/EU and uses lead-free matte tin terminal finish. The SOT109-1 package is qualified per JEDEC J-STD-020 moisture sensitivity level 1 (unlimited floor life at ≤30 °C/85 % RH).
74HC123DB,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HC
- Package/Case:
- 16-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- No
- Propagation Delay:
- 65 ns
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2 V ~ 6 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SSOP
74HC123DB,112 FAQ
1.How can I place an order for 74HC123DB,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC123DB,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC123DB,112 reliable?
The price and inventory of 74HC123DB,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC123DB,112 is usually 5 days.
3.What payment methods are accepted for 74HC123DB,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC123DB,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC123DB,112?
74HC123DB,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC123DB,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC123DB,112?
For technical support, including 74HC123DB,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC123DB,112 requirements.
6.How does Aetrix verify that 74HC123DB,112 is sourced from the original manufacturer or authorized distributors?
All 74HC123DB,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC123DB,112 meets industry standards.
7.What is the process for return or replacement of 74HC123DB,112?
All 74HC123DB,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC123DB,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC123DB,112 part is unused and in its original packaging.
Return procedure for 74HC123DB,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HC123DB,112 Tags

-
SN74LVC1G123DCUR
Texas Instruments
-
CD4047BM96
Texas Instruments

-
SN74LVC1G123DCTR
Texas Instruments
-
CD74HC221M96
Texas Instruments

-
CD14538BE
Texas Instruments

-
SN74LVC1G123YZPR
Texas Instruments

-
SN74LVC1G123DCUT
Texas Instruments
-
MC14538BDR2G
onsemi

-
74VHC123AMX
onsemi

-
LTC6993CS6-2#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-3#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-1#TRMPBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

