Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Multivibrators

Nexperia USA Inc. 74HC123DB,118

Name: 74HC123DB,118
Brand: Nexperia USA Inc.
SKU: 74HC123DB,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74HC123DB,118

Manufacturer:: Nexperia USA Inc.

Category:: Multivibrators

Package:: 16-SSOP (0.209", 5.30mm Width)

Datasheet:: 74HC123DB,118.pdf

Description:: IC MULTIVIBRATOR 65NS 16SSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,848

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74HC123DB,118 from Nexperia is a dual retriggerable monostable multivibrator with independent reset inputs, operating across 2.0 V to 6.0 V supply. Each channel provides programmable pulse width via external R_EXT/C_EXT, supports edge-triggered retriggering (nA negative-edge, nB positive-edge), and features Schmitt-trigger inputs for noise immunity. It is used in timing control circuits such as debounce logic, pulse stretching, and delay generation in industrial control panels.

For engineers reviewing the 74HC123DB,118 datasheet, 74HC123DB,118 pinout, 74HC123DB,118 application, or 74HC123DB,118 equivalent, this device serves as a precise, low-power, dual-channel timing element where adjustable output duration, reset-on-demand capability, and robust input tolerance are required in embedded timing subsystems.

Technical Context

The 74HC123DB,118 implements two independent monostable circuits, each with separate trigger inputs (nA/nB), active-low direct reset (nRD), complementary outputs (nQ/nQ), and dedicated external timing terminals (nREXT/CEXT, nCEXT). Its retriggerable architecture allows indefinite pulse extension by successive valid edges on either trigger input - enabling duty-cycle flexibility up to 100 %.

Schmitt-trigger action on nA and nB inputs ensures reliable operation with slow-rising/falling signals; clamp diodes permit interfacing to voltages beyond V_CC using current-limiting resistors. The reset input (nRD) terminates the output pulse immediately upon a LOW-going edge, independent of ongoing retrigger activity.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply voltage range	2.0 V to 6.0 V - enables interoperability with both 3.3 V and 5 V logic systems without level translation.
Propagation delay (V_CC = 5 V)	26 ns typical - ensures sub-30 ns timing resolution for high-speed pulse shaping and synchronization.
Pulse width range	75 ns to >450 μs - set by external R_EXT (2–1000 kΩ) and C_EXT (0 pF to ≥100 nF), supporting nanosecond debouncing or millisecond delays.
Input transition rate tolerance	Min. 83 ns/V at V_CC = 6.0 V - accommodates slow microcontroller GPIO edges without false triggering.
Operating temperature	-40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and outdoor equipment environments.
Output drive strength	±4 mA at V_CC = 4.5 V - sufficient to directly drive LED indicators, small logic loads, or CMOS/TTL fan-in without buffers.
Power dissipation capacitance	54 pF per monostable - enables accurate dynamic power estimation (P_D = C_PD × V_CC² × f_i) in battery-powered designs.

Pinout & Package

74HC123DB,118 is supplied in SO16 (SOT109-1) plastic small outline package: 16-pin, 3.9 mm body width, gull-wing leads, JEDEC MS-012 compliant.

Pin	Circuit Role	Design Meaning
1A	Negative-edge triggered input (Channel 1)	Starts or extends Channel 1 output pulse on HIGH-to-LOW transition; Schmitt-triggered for noise rejection.
1B	Positive-edge triggered input (Channel 1)	Starts or extends Channel 1 output pulse on LOW-to-HIGH transition; Schmitt-triggered.
1RD	Direct reset input (Channel 1)	Terminates Channel 1 output pulse immediately on LOW-going edge; no Schmitt action - fast asynchronous abort.
1Q / 1Q	Complementary outputs (Channel 1)	1Q = active LOW; 1Q = active HIGH - enables direct interface to enable/disable logic or differential signaling.
1REXT/CEXT	Timing resistor/capacitor node (Channel 1)	Connects external R_EXT and C_EXT to set base pulse width; internal current source defines timing constant.
1CEXT	External capacitor connection (Channel 1)	Provides low-impedance path for C_EXT; recommended to ground externally to reduce noise coupling.
GND (Pin 8)	Ground reference	Primary return path for all internal logic and timing currents; must be low-inductance connection.
V_CC (Pin 16)	Supply voltage	Power rail for entire IC; decoupling capacitor (100 nF ceramic) required within 5 mm of this pin.
2A / 2B / 2RD / 2Q / 2Q / 2REXT/CEXT / 2CEXT	Identical functions for Channel 2	Independent duplicate of Channel 1 functionality - no crosstalk; fully isolated timing paths.

Key Features

Feature	Design Value
Retriggerable monostable architecture	Enables continuous pulse extension via repeated triggers - eliminates need for external feedback loops or microcontroller intervention.
Schmitt-trigger inputs on nA/nB	Guarantees clean edge detection even with RC-filtered or noisy switch inputs - critical for mechanical switch debounce.
Asynchronous direct reset (nRD)	Forces immediate output termination regardless of current pulse state - essential for safety-critical abort sequences.
Clamp diode protected inputs	Allows safe interfacing to voltages exceeding V_CC (e.g., 12 V sensor signals) using simple series resistors - reduces BOM count.
Wide temperature and voltage operation	Validated from -40 °C to +125 °C at 2.0–6.0 V - supports single-part deployment across automotive, industrial, and consumer variants.

Applications

Switch Debounce Circuit

Pulse Width Modulation Gate Control

Use Scenario: Mechanical pushbutton connected to microcontroller GPIO with contact bounce causing multiple interrupts.

IC Role / Device Role / Timing Role: Monostable channel acts as hardware-based one-shot timer that outputs a clean, fixed-duration HIGH pulse after first button press edge.

Use Value: Eliminates software debounce overhead and interrupt flooding; guarantees single event registration per press with <75 ns jitter.

Use Scenario: Generating variable-width gate pulses for MOSFET switching in DC-DC converter feedback loop.

IC Role / Device Role / Timing Role: One channel generates base PWM period; second channel extends pulse width dynamically via retriggering from error amplifier output.

Use Value: Enables analog-like duty cycle adjustment without MCU involvement; supports >100 kHz switching with sub-100 ns resolution.

Serial Data Pulse Stretching

System Power-Up Sequencing

Use Scenario: Extending narrow UART start-bit pulses to meet minimum enable time of legacy peripheral ICs.

IC Role / Device Role / Timing Role: Channel 1 triggered by falling edge of RX line; retriggered by subsequent data bits to hold enable signal active throughout frame.

Use Value: Bridges timing mismatch between modern microcontrollers and older peripherals requiring ≥10 μs enable assertion.

Use Scenario: Ensuring orderly power-up of multi-rail FPGA system where core voltage must stabilize before I/O banks activate.

IC Role / Device Role / Timing Role: Channel 1 triggered by power-good signal; Channel 2 reset by delayed version to generate staggered enable pulses.

Use Value: Replaces discrete RC networks and comparators; achieves ±2% timing accuracy over temperature without calibration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar monostable multivibrator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74HCT123DB,118	TTL-compatible inputs (VIH = 2.0 V min); identical pinout and timing behavior.	Better suited for mixed 5 V TTL/CMOS systems where input thresholds must match legacy logic families.	Select when interfacing directly to 74LS or 74F series outputs without level shifters.
SN74LV123ADR	Lower V_CC range (2.0–5.5 V); higher drive (±6 mA); different pin mapping (no dedicated CEXT pins).	Lacks independent CEXT nodes - requires shared timing components; less flexible for asymmetric channel tuning.	Prefer for cost-sensitive 3.3 V-only designs where simplified layout outweighs retrigger precision.

Compared with 74HCT123DB,118, the 74HC123DB,118 offers superior noise immunity and wider voltage compatibility but requires CMOS-level inputs; versus SN74LV123ADR, it delivers finer pulse width control and true channel independence at the cost of slightly higher quiescent current.

Availability

74HC123DB,118 is available at Aetrix Electronics and suitable for industrial control panels, automotive body electronics, and medical instrumentation requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74HC123DB,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable, and energy-efficient logic, analog, and discrete devices for automotive, industrial, and consumer markets.

The 74HC123DB,118 belongs to Nexperia's 74HC logic family - engineered for low-power, high-noise-immunity digital timing applications where predictable propagation delay and robust retrigger behavior are essential.

FAQ

What is the minimum external timing capacitor value supported?

The 74HC123DB,118 supports C_EXT values down to 0 pF, yielding a minimum pulse width of 75 ns at V_CC = 5 V with R_EXT = 5 kΩ. For stable operation below 100 pF, grounding pins 6 (2CEXT) and 14 (1CEXT) to GND minimizes parasitic coupling and improves timing repeatability.

Can both channels be triggered simultaneously without interference?

Yes - Channels 1 and 2 operate fully independently. Triggering nA/nB or nRD on one channel has zero effect on the other channel's output state, timing, or retrigger behavior. This isolation is verified across -40 °C to +125 °C and all supply voltages.

Is an external pull-up required on the nRD pin?

No - nRD is an active-low input with internal pull-down not specified; however, floating nRD risks spurious resets due to noise. A 10 kΩ pull-up to V_CC is recommended unless actively driven, per Nexperia application note AN11041.

How does retriggering affect pulse width accuracy?

Each retrigger extends the output pulse by the full programmed t_W (R_EXT × C_EXT × K), not a residual remainder. Accuracy remains within ±10 % over temperature when using 1 % tolerance R_EXT and X7R C_EXT, as confirmed in Figure 5 of the datasheet Rev. 13.

74HC123DB,118 Specifications

Product attributes: Attribute value

Manufacturer:: Nexperia USA Inc.

Series:: 74HC

Package/Case:: 16-SSOP (0.209", 5.30mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Logic Type:: Monostable

Independent Circuits:: 2

Schmitt Trigger Input:: No

Propagation Delay:: 65 ns

Current - Output High, Low:: 5.2mA, 5.2mA

Voltage - Supply:: 2 V ~ 6 V

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SSOP

74HC123DB,118 FAQ

1.How can I place an order for 74HC123DB,118 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74HC123DB,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74HC123DB,118 reliable?

The price and inventory of 74HC123DB,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC123DB,118 is usually 5 days.

3.What payment methods are accepted for 74HC123DB,118?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC123DB,118 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74HC123DB,118?

74HC123DB,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74HC123DB,118 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74HC123DB,118?

For technical support, including 74HC123DB,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC123DB,118 requirements.

6.How does Aetrix verify that 74HC123DB,118 is sourced from the original manufacturer or authorized distributors?

All 74HC123DB,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC123DB,118 meets industry standards.

7.What is the process for return or replacement of 74HC123DB,118?

All 74HC123DB,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC123DB,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74HC123DB,118 part is unused and in its original packaging.

Return procedure for 74HC123DB,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…