Nexperia USA Inc. 74HC126DB,112
- Part No.:
- 74HC126DB,112
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74HC126DB,112.pdf
- Description:
- IC BUFFER NON-INVERT 6V 14SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,744
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Product details
Overview
74HC126DB,112 from Nexperia is a quad 3-state buffer/line driver in SO14 (SOT108-1) package, operating from 2.0 V to 6.0 V supply, with CMOS-level inputs, ±35 mA output drive, and propagation delay as low as 9 ns at VCC = 6.0 V. It serves as a bidirectional bus interface or signal isolator in digital logic systems requiring controlled output enable timing.
For engineers reviewing the 74HC126DB,112 datasheet, 74HC126DB,112 pinout, 74HC126DB,112 application, or 74HC126DB,112 equivalent, key selection criteria include 3-state enable timing (ten/tdis ≤ 32 ns), input voltage thresholds (VIH = 4.2 V min at VCC = 6.0 V), thermal rating (-40 °C to +125 °C), and SO14 package compatibility with legacy PCB footprints.
Technical Context
This device implements four independent non-inverting buffers, each with active-HIGH output enable (nOE) controlling high-impedance OFF-state. Input clamp diodes allow safe interfacing to voltages exceeding VCC when used with current-limiting resistors.
It complies with JEDEC JESD7A (2.0–6.0 V) and JESD8C (2.7–3.6 V), supports HBM ESD >2000 V and CDM >1000 V, and delivers guaranteed VOL ≤ 0.4 V at IO = 7.8 mA and VCC = 6.0 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 2.0 V to 6.0 V - Enables direct interface with 3.3 V and 5 V logic domains without level shifters. |
| Propagation Delay | 9 ns (typ) at VCC = 6.0 V, CL = 50 pF - Supports >30 MHz bus operation with tight timing margins. |
| Output Drive | ±35 mA - Sufficient to drive 50-pF loads across full temperature range without external buffering. |
| Input Thresholds | VIH = 4.2 V (min), VIL = 1.8 V (max) at VCC = 6.0 V - Ensures robust noise immunity (>1.2 V DC noise margin). |
| Operating Temperature | -40 °C to +125 °C - Qualified for industrial and extended-temperature embedded control applications. |
| Power Dissipation | 500 mW (max) at Tamb ≤ 100 °C - Allows sustained operation in compact enclosures with minimal heatsinking. |
| ESD Rating | HBM >2000 V, CDM >1000 V - Meets IEC 61000-4-2 system-level ESD robustness requirements. |
Pinout & Package
74HC126DB,112 uses the SO14 (SOT108-1) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads, JEDEC MS-012 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (1OE–4OE) | Active-HIGH output enable inputs - Assert HIGH to activate corresponding buffer output; LOW forces high-impedance state. |
| 2, 5, 9, 12 | nA (1A–4A) | Buffer input terminals - Accept CMOS-level signals; internal clamp diodes permit overvoltage-safe interfacing. |
| 3, 6, 8, 11 | nY (1Y–4Y) | Non-inverting buffered outputs - Deliver rail-to-rail logic levels with 3-state capability per channel. |
| 7 | GND | Ground reference (0 V) - Must be connected to system common ground plane for stable noise performance. |
| 14 | VCC | Positive supply rail - Decoupling capacitor (100 nF ceramic) required within 5 mm of this pin for switching integrity. |
Key Features
| Feature | Design Value |
|---|---|
| Wide Supply Range | 2.0–6.0 V operation enables single-supply use across 3.3 V and 5 V systems without voltage translation. |
| 3-State Output Control | Independent active-HIGH enable per buffer allows dynamic bus arbitration and multi-drop signal routing. |
| Input Clamp Diodes | Integrated clamps support safe interfacing to voltages up to VCC + 0.5 V using external current-limiting resistors. |
| Latch-Up Immunity | Exceeds 100 mA per JESD78 Class II Level B - Prevents destructive latch-up under transient overvoltage conditions. |
| Low Dynamic Power | CPD = 23 pF - Minimizes switching power (PD = CPD × VCC² × fi × N) in high-frequency data paths. |
Applications
| Industrial PLC Backplane Interface | Legacy Microcontroller Bus Expansion |
|---|---|
|
Use Scenario: Isolating and driving address/data lines between CPU and peripheral modules on a DIN-rail mounted PLC backplane. IC Role / Device Role / Timing Role: Quad buffer provides direction-controlled signal isolation and fanout amplification while enabling/disabling segments via OE lines. Use Value: 3-state outputs prevent bus contention during hot-swap module insertion; -40 °C to +125 °C rating ensures reliability in uncooled control cabinets. |
Use Scenario: Expanding GPIO count of an 8-bit microcontroller by adding parallel I/O ports via 8-bit latched bus interface. IC Role / Device Role / Timing Role: Acts as bi-directional bus driver with OE synchronized to microcontroller's WR/RD strobes for clean read/write handshaking. Use Value: 9 ns propagation delay meets setup/hold timing for 12 MHz MCU buses; SO14 footprint matches legacy board layouts. |
| Test Equipment Signal Routing Matrix | Automated Test Fixture Logic Level Translation |
|
Use Scenario: Configurable signal path selection in modular ATE systems where DUT signals are routed through programmable logic banks. IC Role / Device Role / Timing Role: Provides channelized enable-controlled signal pass-through with precise timing alignment across all four buffers. Use Value: Matched enable-to-output delays (ten/tdis ≤ 32 ns) ensure deterministic skew across parallel test channels. |
Use Scenario: Adapting 5 V logic outputs from legacy instrumentation to 3.3 V FPGA inputs in production test fixtures. IC Role / Device Role / Timing Role: Functions as level-tolerant buffer: 5 V inputs safely accepted via clamp diodes; outputs swing rail-to-rail at 3.3 V supply. Use Value: Eliminates need for discrete level-shifters; VIH = 4.2 V (min) at VCC = 5 V ensures reliable recognition of TTL-compatible inputs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HC125DB,112 | Inverting output polarity (nY = NOT nA); identical pinout, timing, and supply specs. | Requires logic inversion in signal path; unsuitable where non-inverting topology is mandated by protocol. | Select only if system-level logic requires inverted buffering; otherwise, 74HC126DB,112 maintains signal polarity. |
| SN74LVC126APWR | 3.3 V only (1.65–3.6 V), lower VIL/VOL, faster tpd (3.5 ns typ), TSSOP14 package. | Better suited for modern low-voltage FPGAs; incompatible with 5 V systems or SO14-restricted boards. | Choose for new 3.3 V designs needing higher speed; retain 74HC126DB,112 for 5 V compatibility or SO14 footprint continuity. |
Compared with 74HC126DB,112, the 74HC125DB,112 offers functional equivalence except for output inversion, while SN74LVC126APWR trades 5 V tolerance and SO14 compatibility for speed and 3.3 V efficiency-making each optimal for distinct voltage and layout constraints.
Availability
74HC126DB,112 is available at Aetrix Electronics and suitable for industrial PLC backplanes, legacy microcontroller bus expansion, automated test equipment signal routing, and automated test fixture logic level translation requiring stable component supply and long-term obsolescence management.
Supply support for 74HC126DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions with focus on efficiency, reliability, and manufacturability for industrial and consumer applications.
The 74HC126 series belongs to Nexperia's standard logic portfolio, designed specifically for robust, drop-in replacement of legacy 74-series logic in industrial control, instrumentation, and interface applications demanding wide voltage range and high-temperature operation.
FAQ
What is the maximum clock frequency supported by 74HC126DB,112 in a data bus application?
The 74HC126DB,112 does not operate as a clocked device but as a combinational buffer. Its 9 ns typical propagation delay at VCC = 6.0 V supports reliable data transfer up to approximately 30 MHz in synchronous bus systems, assuming adequate setup/hold margins and 50 pF load. Maximum usable frequency depends on total path delay including PCB traces and downstream loading.
Can 74HC126DB,112 interface safely with 5 V inputs while powered from a 3.3 V supply?
No. The 74HC126DB,112 requires VCC ≥ 4.5 V to reliably recognize 5 V inputs as HIGH (VIH min = 4.2 V at VCC = 6.0 V, but drops to 3.15 V at VCC = 4.5 V). At 3.3 V supply, VIH max is 2.4 V - insufficient for 5 V logic. Use clamp diodes only with current-limiting resistors when input exceeds VCC by ≤0.5 V.
How does the 3-state enable timing affect bus arbitration in multi-driver systems?
Enable time (ten ≤ 32 ns) and disable time (tdis ≤ 32 ns) determine minimum dead-time between driver transitions. In shared-bus systems, these values define the shortest safe interval before the next driver can assert, preventing bus contention. Matching ten/tdis across channels ensures deterministic turn-off/turn-on sequencing critical for glitch-free arbitration.
Is 74HC126DB,112 automotive-qualified?
No. Per Nexperia's legal disclaimers, 74HC126DB,112 is not automotive-qualified. It is specified for industrial temperature range (-40 °C to +125 °C) but lacks AEC-Q100 qualification, automotive-grade screening, or failure rate reporting. Use only in non-safety-critical industrial or commercial applications.
74HC126DB,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HC
- Package/Case:
- 14-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SSOP
74HC126DB,112 FAQ
1.How can I place an order for 74HC126DB,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC126DB,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC126DB,112 reliable?
The price and inventory of 74HC126DB,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC126DB,112 is usually 5 days.
3.What payment methods are accepted for 74HC126DB,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC126DB,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC126DB,112?
74HC126DB,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC126DB,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC126DB,112?
For technical support, including 74HC126DB,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC126DB,112 requirements.
6.How does Aetrix verify that 74HC126DB,112 is sourced from the original manufacturer or authorized distributors?
All 74HC126DB,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC126DB,112 meets industry standards.
7.What is the process for return or replacement of 74HC126DB,112?
All 74HC126DB,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC126DB,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC126DB,112 part is unused and in its original packaging.
Return procedure for 74HC126DB,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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