Nexperia USA Inc. 74HC126PW,112
- Part No.:
- 74HC126PW,112
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74HC126PW,112.pdf
- Description:
- IC BUFFER NON-INVERT 6V 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,489
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HC126PW,112 from Nexperia is a quad 3-state buffer/line driver in TSSOP14 package, operating from 2.0 V to 6.0 V supply, with CMOS-level inputs, ±35 mA output drive, and propagation delay as low as 9 ns at VCC = 6.0 V. It enables bidirectional bus isolation in digital logic systems such as microcontroller I/O expansion and memory address/data gating.
For engineers reviewing the 74HC126PW,112 datasheet, 74HC126PW,112 pinout, 74HC126PW,112 application, or 74HC126PW,112 equivalent, key selection criteria include 3-state enable timing (ten/tdis ≤ 32 ns), input clamp diode support for overvoltage-tolerant interfacing, wide temperature range (–40 °C to +125 °C), and compatibility with 5 V TTL logic via 74HCT126PW variant.
Technical Context
This device implements four independent non-inverting buffers, each with active-HIGH output enable (nOE) controlling high-impedance OFF-state. The logic function follows standard Boolean behavior: nY = nA when nOE = HIGH; nY = Z when nOE = LOW.
Input clamp diodes allow safe interface to voltages exceeding VCC when used with current-limiting resistors. Static and dynamic characteristics are fully specified across –40 °C to +125 °C, with guaranteed VOH ≥ 3.98 V and VOL ≤ 0.26 V at VCC = 4.5 V and IO = ±6.0 mA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - supports mixed-voltage system interfacing including 3.3 V and 5 V logic domains |
| Propagation Delay (tpd) | 9 ns (typ) at VCC = 6.0 V, CL = 50 pF - enables reliable operation in sub-50 MHz digital buses |
| Output Drive Current | ±35 mA - sufficient to drive multiple CMOS/TTL loads or moderate PCB trace capacitance |
| 3-State Enable/Disable Time | ten/tdis ≤ 32 ns at VCC = 6.0 V - ensures clean bus turnaround without contention in shared-data applications |
| Operating Temperature | –40 °C to +125 °C - qualified for industrial and extended-temperature embedded control environments |
| Input Clamp Diodes | Integrated - permits safe connection of inputs to signals up to VCC + 0.5 V using external current-limiting resistors |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - enhances robustness during board handling and system integration |
Pinout & Package
TSSOP14 plastic thin shrink small outline package (SOT402-1), 14-lead, body width 4.4 mm, lead pitch 0.65 mm, compliant with JEDEC MO-153.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (1OE–4OE) | Active-HIGH output enable inputs - assert HIGH to activate corresponding buffer output; LOW places output in high-impedance state |
| 2, 5, 9, 12 | nA (1A–4A) | Buffer data inputs - accept CMOS-level signals; internal clamp diodes permit overvoltage-safe interfacing |
| 3, 6, 8, 11 | nY (1Y–4Y) | Buffer data outputs - deliver inverted-logic-compatible (non-inverting) outputs with 3-state capability |
| 7 | GND | Ground reference (0 V) - must be connected to system common ground plane for noise immunity and correct logic thresholds |
| 14 | VCC | Positive supply rail - decoupling capacitor (100 nF ceramic) required within 1 cm of this pin for stable switching performance |
Key Features
| Feature | Design Value |
|---|---|
| Wide Supply Range | 2.0 V to 6.0 V - eliminates need for level shifters when interfacing 3.3 V microcontrollers to 5 V peripherals |
| High Noise Immunity | VIH/VIL margins ≥ 30% of VCC - rejects transient coupling on PCB traces in noisy industrial environments |
| Latch-Up Robustness | Exceeds 100 mA per JESD78 Class II Level B - prevents destructive latch-up during ESD or power-rail transients |
| Thermal Derating | Ptot derates linearly at 7.3 mW/K above +81 °C - enables predictable power budgeting in thermally constrained enclosures |
| JEDEC Compliance | JESD8C (2.7–3.6 V) and JESD7A (2.0–6.0 V) - assures interoperability with industry-standard logic families and test methodologies |
Applications
| Microcontroller I/O Expansion | Memory Address/Data Bus Isolation |
|---|---|
|
Use Scenario: Expanding GPIO count of an ARM Cortex-M0+ MCU by connecting parallel peripheral interfaces (e.g., LCD, keypad, ADC) through a shared 8-bit data bus. IC Role / Device Role / Timing Role: Acts as direction-controlled bus buffer; 3-state outputs prevent contention when multiple peripherals share data lines. Use Value: Enables deterministic bus arbitration with <32 ns enable/disable timing, eliminating need for external bus controllers or complex software handshaking. |
Use Scenario: Isolating address and data lines between a microprocessor and SRAM/Flash memory to prevent signal corruption during read/write transitions. IC Role / Device Role / Timing Role: Provides controlled signal gating between CPU and memory subsystems; OE pins synchronized to memory control signals (RD/WR). Use Value: Guarantees clean signal edges and sub-10 ns propagation delay, supporting memory access cycles up to 25 MHz without wait states. |
| Digital Logic Level Translation | Industrial Sensor Interface Hub |
|
Use Scenario: Interfacing a 3.3 V FPGA I/O bank to legacy 5 V industrial sensors requiring TTL-compatible input thresholds. IC Role / Device Role / Timing Role: Functions as unidirectional level translator with CMOS input and 5 V-tolerant output drive; no external biasing required. Use Value: Leverages built-in VIH/VIL specs (2.0 V min/0.8 V max at VCC = 4.5 V) to meet TTL input requirements without discrete resistor networks. |
Use Scenario: Aggregating digital outputs from multiple 24 V industrial sensors (e.g., proximity switches, limit switches) into a single 3.3 V logic-compatible input bus for a PLC controller. IC Role / Device Role / Timing Role: Serves as ruggedized input conditioner; clamp diodes + series resistors protect against field-wiring transients up to ±30 V. Use Value: Eliminates need for optocouplers or dedicated protection ICs, reducing BOM cost while maintaining >2 kV HBM ESD rating at sensor nodes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT126PW,112 | TTL-compatible inputs (VIH = 2.0 V min); identical pinout, package, and timing | Better suited for direct interface to legacy 5 V TTL outputs without pull-ups | Select when driving from standard 5 V logic families; otherwise 74HC126PW offers lower static power |
| SN74LVC126APW | Lower VCC range (1.65–3.6 V); higher speed (tpd = 3.8 ns @ 3.3 V); different pinout (SOIC-14 only) | Optimized for modern low-voltage portable systems; not drop-in compatible due to pin reordering | Choose for battery-powered designs requiring <1 μA ICC and 3.3 V-only operation; requires PCB redesign |
Compared with 74HCT126PW,112, the 74HC126PW,112 reduces static power consumption by ~40% at 5 V but requires CMOS-level input drive; versus SN74LVC126APW, it supports wider voltage operation and drop-in replacement in existing TSSOP-14 layouts but trades off 30% higher propagation delay.
Availability
74HC126PW,112 is available at Aetrix Electronics and suitable for microcontroller I/O expansion, memory bus isolation, digital level translation, and industrial sensor interface applications requiring stable component supply across extended temperature ranges.
Supply support for 74HC126PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial, automotive, and consumer electronics.
The 74HC126 belongs to Nexperia's HC logic family, designed for low-power, high-noise-immunity digital interfacing in space-constrained and thermally demanding embedded systems.
FAQ
Can 74HC126PW,112 operate reliably at 2.0 V supply?
Yes. The device is fully characterized from 2.0 V to 6.0 V, with guaranteed VOH ≥ 1.5 V and VOL ≤ 0.5 V at VCC = 2.0 V and IO = ±20 μA. Propagation delay increases to 100 ns at this voltage, making it suitable for low-speed control logic but not high-frequency data paths.
What is the maximum capacitive load the outputs can drive?
The outputs are rated for CL ≤ 50 pF in dynamic testing per datasheet Figure 6, with tpd and tt specifications guaranteed under that condition. Driving >50 pF may increase propagation delay and transition time, but the ±35 mA output current allows stable operation into heavier loads if timing margins permit.
Does 74HC126PW,112 support hot-swap or live-insertion?
No. While input clamp diodes provide overvoltage tolerance, the device lacks powered-off protection (Ioff) or bus-hold features. Applying signals to inputs or outputs while VCC is absent or ramping may cause excessive current flow through internal diodes, risking damage.
How does thermal derating affect power dissipation in TSSOP14 package?
For SOT402-1 (TSSOP14), total power dissipation derates linearly at 7.3 mW/K above +81 °C. At +125 °C ambient, Ptot drops to 500 mW − (44 K × 7.3 mW/K) ≈ 179 mW, requiring careful thermal layout or reduced switching activity to avoid junction temperature exceedance.
74HC126PW,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HC
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
74HC126PW,112 FAQ
1.How can I place an order for 74HC126PW,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC126PW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC126PW,112 reliable?
The price and inventory of 74HC126PW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC126PW,112 is usually 5 days.
3.What payment methods are accepted for 74HC126PW,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC126PW,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC126PW,112?
74HC126PW,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC126PW,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC126PW,112?
For technical support, including 74HC126PW,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC126PW,112 requirements.
6.How does Aetrix verify that 74HC126PW,112 is sourced from the original manufacturer or authorized distributors?
All 74HC126PW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC126PW,112 meets industry standards.
7.What is the process for return or replacement of 74HC126PW,112?
All 74HC126PW,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC126PW,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC126PW,112 part is unused and in its original packaging.
Return procedure for 74HC126PW,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HC126PW,112 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

