Nexperia USA Inc. 74HC138BQ-Q100,115
- Part No.:
- 74HC138BQ-Q100,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-VFQFN Exposed Pad
- Datasheet:
-
74HC138BQ-Q100,115.pdf
- Description:
- IC DECODER/DEMUX 1X3:8 16DHVQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74HC138BQ-Q100 from Nexperia is an automotive-grade 3-to-8 line inverting decoder/demultiplexer with three active-LOW enable inputs (E1, E2), one active-HIGH enable input (E3), and eight mutually exclusive active-LOW outputs (Y0–Y7). It operates across 2.0–6.0 V supply, supports -40 °C to +125 °C ambient, and features CMOS-level inputs for low power and high noise immunity. It is used in automotive memory chip select decoding and address demultiplexing.
For engineers reviewing the 74HC138BQ-Q100 datasheet, 74HC138BQ-Q100 pinout, 74HC138BQ-Q100 application, or 74HC138BQ-Q100 equivalent, key selection criteria include its AEC-Q100 Grade 1 qualification, DHVQFN16 package with side-wettable flanks, propagation delay down to 12 ns at VCC = 6.0 V, and compatibility with both HC and HCT logic families via dual part numbering.
Technical Context
The device implements a standard 3-input binary decoder with inverted output logic: only one of Y0–Y7 goes LOW when all enables are satisfied (E1 = LOW, E2 = LOW, E3 = HIGH) and a unique A2:A0 combination is present. Its multiple enable architecture enables cascading-e.g., four units plus one inverter achieve 1-of-32 decoding without external logic.
Input clamping diodes allow safe interfacing to voltages exceeding VCC when used with current-limiting resistors. All inputs tolerate overvoltage conditions per JESD7A, and outputs drive ±25 mA with guaranteed VOL ≤ 0.4 V at IO = 5.2 mA and VCC = 6.0 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - supports wide-battery automotive rails and mixed-voltage system integration |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive environments per AEC-Q100 Grade 1 |
| Propagation Delay (tpd) | 12 ns (max) at VCC = 6.0 V, CL = 50 pF - enables timing-critical address decoding in fast microcontroller systems |
| Output Drive Strength | ±25 mA - sufficient to directly drive LEDs, small logic loads, or enable lines of downstream ICs |
| Input Logic Compatibility | CMOS-level (74HC variant) - VIH ≥ 4.2 V, VIL ≤ 1.8 V at VCC = 6.0 V - ensures robust noise margin in noisy automotive harnesses |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - meets stringent automotive ESD immunity requirements per JS-001/JS-002 |
| Power Dissipation | Ptot = 500 mW (derated above 106 °C) - thermal design accommodates compact DHVQFN16 layout with side-wettable flanks |
Pinout & Package
DHVQFN16 package (SOT763-1): 2.5 × 3.5 × 0.85 mm body, no leads, 16 terminals, side-wettable flanks for AOI-compatible solder joint inspection. Exposed thermal pad (terminal 1) is electrically isolated unless connected to GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Thermal pad (GND-optional) | Non-electrical thermal interface; may be left floating or tied to GND for improved heat dissipation |
| 2 | A1 | Binary-weighted address input (2¹); sampled synchronously with enable conditions |
| 3 | A2 | Binary-weighted address input (2²); determines MSB of decoded 3-bit word |
| 4 | E1 | Active-LOW enable input; must be LOW with E2 for decode activation |
| 5 | E2 | Active-LOW enable input; paired with E1 for multi-chip expansion control |
| 6 | E3 | Active-HIGH enable input; enables full decode only when HIGH |
| 7 | Y7 | Active-LOW decoded output (A2:A1:A0 = 111); sinks current when selected |
| 8 | GND | Reference ground (0 V); return path for all internal logic and I/O currents |
| 9 | Y6 | Active-LOW decoded output (A2:A1:A0 = 110); mutually exclusive with other Yn |
| 10 | Y5 | Active-LOW decoded output (A2:A1:A0 = 101); asserted only when address matches |
| 11 | Y4 | Active-LOW decoded output (A2:A1:A0 = 100); used for memory bank selection |
| 12 | Y3 | Active-LOW decoded output (A2:A1:A0 = 011); compatible with TTL load thresholds |
| 13 | Y2 | Active-LOW decoded output (A2:A1:A0 = 010); drives enable lines of peripheral ICs |
| 14 | Y1 | Active-LOW decoded output (A2:A1:A0 = 001); provides discrete signal routing |
| 15 | Y0 | Active-LOW decoded output (A2:A1:A0 = 000); default selection when all address bits LOW |
| 16 | VCC | Positive supply rail (2.0–6.0 V); powers internal CMOS circuitry and output drivers |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Grade 1 qualification | Validated for automotive use from -40 °C to +125 °C with lifetime reliability testing |
| Multiple enable architecture | E1/E2 (active-LOW) + E3 (active-HIGH) allows hierarchical decoding and seamless 1-of-32 expansion |
| Inverting active-LOW outputs | Y0–Y7 assert LOW on match - directly interfaces with active-LOW chip selects (e.g., SRAM, Flash) |
| DHVQFN16 with side-wettable flanks | Enables automated optical inspection of solder joints - critical for zero-defect automotive manufacturing |
| Input clamp diodes | Permits safe interfacing to signals up to VCC + 0.5 V using series resistors - eliminates need for external protection |
Applications
| Automotive Body Control Module (BCM) | Infotainment System Memory Expansion |
|---|---|
Use Scenario: Selecting among 8 discrete lighting driver ICs (e.g., LED matrix controllers) based on CAN-commanded lighting mode. IC Role / Device Role / Timing Role: Address decoder mapping 3-bit command field to individual driver enable lines; propagation delay <15 ns ensures real-time response. Use Value: Eliminates discrete logic gates; reduces BOM count and PCB area while maintaining AEC-Q100 compliance. | Use Scenario: Expanding microcontroller address space to access multiple SPI Flash and SRAM devices in head unit firmware storage. IC Role / Device Role / Timing Role: Chip select decoder generating eight independent /CS signals; active-LOW outputs match standard memory interface polarity. Use Value: Enables single MCU to manage up to eight memory devices without address bus contention or timing skew. |
| ADAS Camera Sensor Interface | Electric Power Steering (EPS) Motor Driver Sequencing |
Use Scenario: Routing configuration commands from SoC to eight image sensor sub-modules (e.g., surround-view cameras). IC Role / Device Role / Timing Role: Demultiplexer using E3 as data input and A2:A0 as channel address; supports burst-mode register writes. Use Value: Reduces interconnect complexity versus parallel buses; maintains signal integrity via short trace lengths to each sensor. | Use Scenario: Enabling sequential activation of gate drivers for three-phase inverter stages in EPS motor control. IC Role / Device Role / Timing Role: Decoder driving enable inputs of six half-bridge drivers (two per phase) with precise mutual exclusion. Use Value: Prevents shoot-through by guaranteeing only one driver pair is active per decoded state - critical for functional safety. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT138BQ-Q100 | TTL-compatible inputs (VIH = 2.0 V min at VCC = 4.5 V); identical pinout, package, and timing | Required when interfacing with legacy 5 V TTL logic; higher input current vs. HC variant | Select when driving from 5 V microcontrollers or legacy logic families without level shifters |
| SN74LS138DR | Bipolar TTL technology; VCC = 4.75–5.25 V only; slower (tpd ≈ 22 ns); no AEC-Q100 qualification | Legacy industrial designs; not suitable for automotive or wide-VCC applications | Use only in non-automotive, 5 V-only systems where HC/HCT speed or qualification is unnecessary |
Compared with 74HCT138BQ-Q100, the HC version offers lower static current and wider voltage flexibility but requires CMOS-compatible drivers; SN74LS138DR lacks automotive qualification, thermal performance, and supply range - making it unsuitable for new automotive designs.
Availability
74HC138BQ-Q100 is available at Aetrix Electronics and suitable for automotive body control modules, infotainment memory expansion, and ADAS sensor interface applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74HC138BQ-Q100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for automotive, industrial, and consumer applications.
The 74HC138-Q100 belongs to Nexperia's automotive-qualified logic family, designed specifically for reliable signal routing, address decoding, and chip select generation in harsh-temperature vehicle subsystems.
FAQ
What is the maximum clock/data rate supported by the 74HC138BQ-Q100?
The 74HC138BQ-Q100 is not a clocked device and has no clock input; it is combinational logic. Its maximum usable switching rate is determined by propagation delay and transition time: tpd ≤ 38 ns and tt ≤ 19 ns at VCC = 6.0 V, enabling reliable operation with address changes up to ~12 MHz in worst-case timing paths. System-level timing must account for setup/hold margins relative to enable assertion.
Can the 74HC138BQ-Q100 be used as a demultiplexer, and how?
Yes - configure one active-LOW enable input (e.g., E1) as the data input, hold the other two enables (E2 = LOW, E3 = HIGH) constant, and apply A2:A0 as the 3-bit channel select. The selected Yn output mirrors the inverted E1 signal. This provides 1-to-8 demux functionality with guaranteed mutual exclusivity and no additional components required.
Is the thermal pad (pin 1) required to be soldered or grounded?
No - terminal 1 is a non-electrical thermal pad with no electrical requirement. It may be left unsoldered, floated, or connected to GND for enhanced thermal performance. If soldered, the land must remain electrically isolated unless explicitly tied to GND; it is not internally connected to any circuit node.
How does the 74HC138BQ-Q100 differ from the 74HC138D-Q100?
The 74HC138BQ-Q100 uses a DHVQFN16 package (SOT763-1) with side-wettable flanks for AOI, measuring 2.5 × 3.5 × 0.85 mm. The 74HC138D-Q100 uses SO16 (SOT109-1), 10.0 × 3.9 × 1.75 mm. Both share identical logic, timing, and AEC-Q100 qualification, but BQ enables higher-density automotive PCB layouts and automated solder-joint inspection.
74HC138BQ-Q100,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HC
- Package/Case:
- 16-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-DHVQFN (2.5x3.5)
74HC138BQ-Q100,115 FAQ
1.How can I place an order for 74HC138BQ-Q100,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC138BQ-Q100,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC138BQ-Q100,115 reliable?
The price and inventory of 74HC138BQ-Q100,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC138BQ-Q100,115 is usually 5 days.
3.What payment methods are accepted for 74HC138BQ-Q100,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC138BQ-Q100,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC138BQ-Q100,115?
74HC138BQ-Q100,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC138BQ-Q100,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC138BQ-Q100,115?
For technical support, including 74HC138BQ-Q100,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC138BQ-Q100,115 requirements.
6.How does Aetrix verify that 74HC138BQ-Q100,115 is sourced from the original manufacturer or authorized distributors?
All 74HC138BQ-Q100,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC138BQ-Q100,115 meets industry standards.
7.What is the process for return or replacement of 74HC138BQ-Q100,115?
All 74HC138BQ-Q100,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC138BQ-Q100,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC138BQ-Q100,115 part is unused and in its original packaging.
Return procedure for 74HC138BQ-Q100,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HC138BQ-Q100,115 Tags
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SN74HC138DR
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