My Inquiry
My Account
NXP Semiconductors 74HC138D/AUJ
- Part No.:
- 74HC138D/AUJ
- Manufacturer:
- NXP Semiconductors
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74HC138D/AUJ.pdf
- Description:
- IC DECODER/DEMUX 1 X 3:8 16SO
- Quantity:
- Payment:
- Shipping:
Inventory:3,254
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HC138D/AUJ from Nexperia is a 3-to-8 line inverting decoder/demultiplexer with CMOS-level inputs, operating from 2.0 V to 6.0 V supply, featuring three enable inputs (E1, E2 active LOW; E3 active HIGH) and eight mutually exclusive active LOW outputs (Y0–Y7). It decodes binary address inputs A0–A2 for memory chip select decoding and supports parallel expansion to 1-of-32 decoding using four ICs and one inverter.
For engineers reviewing the 74HC138D/AUJ datasheet, 74HC138D/AUJ pinout, 74HC138D/AUJ application, or 74HC138D/AUJ equivalent, key selection criteria include its wide VCC range (2.0–6.0 V), propagation delay of 12–45 ns (VCC = 4.5–6.0 V), -40 °C to +125 °C temperature rating, SO16 package compatibility, and TTL-input compatibility via the 74HCT138 variant.
Technical Context
The 74HC138D/AUJ implements a standard 3-input binary-to-8-output decoding logic with strict mutual exclusivity: only one output goes LOW when all enables are satisfied (E1 = LOW, E2 = LOW, E3 = HIGH). Its enable architecture allows cascading without external logic-E1/E2 serve as group-select lines while E3 acts as global strobe.
Input clamp diodes permit interfacing to voltages exceeding VCC when used with current-limiting resistors. The device lacks 3-state outputs, so all eight Yx outputs are push-pull with defined HIGH/LOW states under valid enable conditions-no high-impedance mode is supported.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage (VCC) | 2.0 V to 6.0 V - Enables direct interface with 3.3 V and 5 V logic systems without level shifters. |
| Propagation Delay (tpd) | 12 ns (typ, VCC = 6.0 V, CL = 50 pF) - Supports reliable operation up to ~40 MHz address switching in critical timing paths. |
| Output Drive | ±4.0 mA (VCC = 4.5 V) - Sufficient to drive multiple 74HC-series inputs or small LED loads via external current-limiting resistors. |
| Operating Temperature | -40 °C to +125 °C - Qualified for industrial and extended-temperature embedded control applications. |
| Input Logic Levels | CMOS-compatible (VIH ≥ 3.15 V @ VCC = 4.5 V; VIL ≤ 1.35 V) - Ensures noise margin >1.3 V at nominal 4.5 V supply. |
| Power Dissipation Capacitance (CPD) | 67 pF - Used to calculate dynamic power: PD = CPD × VCC² × fi × N, enabling accurate thermal budgeting. |
Pinout & Package
74HC138D/AUJ is supplied in the SO16 (SOT109-1) plastic small outline package: 16-pin, 3.9 mm body width, gull-wing leads, JEDEC MS-012 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A0) | Address input LSB | Binary weight 2⁰; latched on enable activation for Y0–Y7 output selection. |
| 2 (A1) | Address input | Binary weight 2¹; must be stable before enable assertion to avoid glitched outputs. |
| 3 (A2) | Address input MSB | Binary weight 2²; determines top-half (Y4–Y7) vs bottom-half (Y0–Y3) output activation. |
| 4 (E1) | Enable input (active LOW) | Global group enable; tied LOW with pull-down or controller GPIO to activate decoding function. |
| 5 (E2) | Enable input (active LOW) | Secondary group enable; used with E1 for hierarchical decoding in multi-chip systems. |
| 6 (E3) | Enable input (active HIGH) | Strobe input; often driven by chip-select signal to gate decoder output activity synchronously. |
| 7 (Y0) | Output (active LOW) | Selected when A2A1A0 = 000 and enables active; sinks current when asserted. |
| 8 (GND) | Ground reference | 0 V return path for all internal logic and output drivers; requires low-impedance PCB plane. |
| 9 (Y1) | Output (active LOW) | Selected when A2A1A0 = 001; shares same timing and drive strength as Y0–Y7. |
| 10 (Y2) | Output (active LOW) | Selected when A2A1A0 = 010; electrically identical to other Yx outputs. |
| 11 (Y3) | Output (active LOW) | Selected when A2A1A0 = 011; no internal differentiation between Y outputs. |
| 12 (Y4) | Output (active LOW) | Selected when A2A1A0 = 100; supports memory bank selection in 8-bit microcontroller systems. |
| 13 (Y5) | Output (active LOW) | Selected when A2A1A0 = 101; used for peripheral I/O decode in FPGA/CPLD glue logic. |
| 14 (Y6) | Output (active LOW) | Selected when A2A1A0 = 110; compatible with standard 74-series load fanout (10 LSTTL). |
| 15 (Y7) | Output (active LOW) | Selected when A2A1A0 = 111; final output in sequence; matches propagation delay spec across all Yx. |
| 16 (VCC) | Supply voltage | Primary power rail; requires local 100 nF ceramic decoupling within 5 mm of pin 16. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (2.0–6.0 V) | Supports mixed-voltage system integration-direct connection to 2.5 V, 3.3 V, and 5 V domains without regulators. |
| Inverting active LOW outputs | Directly drives common-cathode LED arrays or enables NMOS/N-channel load switches without inverters. |
| Multiple enable architecture | E1/E2/E3 allow hierarchical decoding: two 74HC138D/AUJ ICs can form a 1-of-16 decoder with no external gates. |
| Clamp diode protected inputs | Permits safe interfacing to 12 V or 24 V control signals using series current-limiting resistors (e.g., 10 kΩ). |
| High noise immunity | Guaranteed VIH/VIL margins exceed 40% of VCC across full temperature range, reducing susceptibility to EMI-induced glitches. |
Applications
| Memory Address Decoding | Peripheral I/O Selection |
|---|---|
Use Scenario: Selecting one of eight SRAM or EEPROM chips in an 8-bit microcontroller system with limited address lines. IC Role / Device Role / Timing Role: 74HC138D/AUJ acts as address-space partitioner, asserting individual chip-select (CS#) lines based on upper address bits A0–A2. Use Value: Eliminates need for discrete logic or larger CPLDs; reduces BOM count and PCB area versus NAND-based decoding. |
Use Scenario: Routing UART, SPI, or GPIO signals to one of eight sensors or actuators in an industrial PLC module. IC Role / Device Role / Timing Role: 74HC138D/AUJ serves as data-path selector, enabling only the target peripheral's receive/transmit lines during communication. Use Value: Provides deterministic, glitch-free channel isolation with sub-15 ns propagation delay-critical for real-time sensor polling. |
| LED Segment Control | FPGA Configuration Glue Logic |
Use Scenario: Driving eight 7-segment LED displays multiplexed via common-anode configuration. IC Role / Device Role / Timing Role: 74HC138D/AUJ generates active LOW digit-enable signals synchronized to display refresh clock. Use Value: Delivers precise, simultaneous digit selection with matched output timing-prevents ghosting or flicker in high-brightness displays. |
Use Scenario: Translating FPGA I/O bank select signals into dedicated configuration enable lines for multiple daughterboards. IC Role / Device Role / Timing Role: 74HC138D/AUJ functions as static configuration decoder, asserting board-specific CONFIG_EN# lines during power-up initialization. Use Value: Enables hot-swap-ready modular hardware design with zero FPGA resource usage for basic enable routing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT138D | TTL-compatible inputs (VIH = 2.0 V min @ VCC = 4.5–5.5 V); otherwise identical pinout, timing, and function. | Required when driving from legacy 5 V TTL or LSTTL sources where HC-level thresholds would cause misreads. | Select 74HCT138D only if interfacing with non-CMOS logic families; otherwise 74HC138D offers superior noise margin. |
| SN74LS138N | Bipolar TTL technology; VCC = 4.75–5.25 V only; higher ICC (19 mA typ), slower tpd (22–35 ns), and no clamp diodes. | Suitable only in legacy 5 V-only systems with existing LS-family designs; incompatible with 3.3 V or mixed-voltage operation. | Choose SN74LS138N only for drop-in replacement in obsolete LS-based boards; not recommended for new designs due to power and voltage limitations. |
Compared with 74HCT138D and SN74LS138N, the 74HC138D/AUJ delivers optimal balance of voltage flexibility (2.0–6.0 V), low static current (<160 μA), and robust ESD protection (HBM >2000 V), making it the preferred choice for modern low-power, multi-rail embedded systems.
Availability
74HC138D/AUJ is available at Aetrix Electronics and suitable for memory address decoding, peripheral I/O selection, LED multiplexing, and FPGA configuration glue logic requiring stable component supply across industrial temperature ranges.
Supply support for 74HC138D/AUJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer applications.
The 74HC138D/AUJ belongs to Nexperia's 74HC logic family, designed for low-power, high-noise-immunity digital interfacing in space-constrained and thermally demanding environments.
FAQ
What is the maximum supply voltage for the 74HC138D/AUJ?
The absolute maximum supply voltage (VCC) for the 74HC138D/AUJ is +7.0 V, but the recommended operating range is 2.0 V to 6.0 V per the datasheet. Operation above 6.0 V risks accelerated aging and violates JEDEC JESD7A compliance; sustained use at 7.0 V may cause permanent damage. For reliable long-term performance, maintain VCC ≤ 6.0 V.
Does the 74HC138D/AUJ support 3-state outputs?
No, the 74HC138D/AUJ does not feature 3-state outputs. All eight Y0–Y7 outputs are push-pull and always assert either HIGH or LOW depending on enable and address conditions-there is no high-impedance (Hi-Z) state. This distinguishes it from variants like the 74HC238, which adds output enable control.
Can the 74HC138D/AUJ be used as a demultiplexer?
Yes, the 74HC138D/AUJ can function as an 1-to-8 demultiplexer: apply the data signal to one active LOW enable input (e.g., E1), use the remaining enables (E2, E3) as strobes, and route A0–A2 as select lines. The selected Yx output mirrors the inverted data state-making it suitable for serial-to-parallel distribution in control logic.
What is the propagation delay of the 74HC138D/AUJ at 3.3 V supply?
The datasheet does not specify propagation delay at exactly 3.3 V; however, interpolation between published values shows tpd ≈ 18–22 ns (max) at VCC = 3.3 V and CL = 50 pF, based on the 2.0 V (150 ns max) and 4.5 V (30 ns max) curves. For design-critical timing, verify with actual measurement or use the 4.5 V spec as conservative bound.
Is the 74HC138D/AUJ pin-compatible with the 74HCT138D?
Yes, the 74HC138D/AUJ and 74HCT138D share identical SO16 pinout, package dimensions, and functional behavior-including enable polarity, output inversion, and address mapping. They differ only in input threshold specifications (CMOS vs TTL levels), allowing direct PCB-level substitution when logic family compatibility is confirmed.
74HC138D/AUJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
74HC138D/AUJ FAQ
1.How can I place an order for 74HC138D/AUJ through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC138D/AUJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC138D/AUJ reliable?
The price and inventory of 74HC138D/AUJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC138D/AUJ is usually 5 days.
3.What payment methods are accepted for 74HC138D/AUJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC138D/AUJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC138D/AUJ?
74HC138D/AUJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC138D/AUJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC138D/AUJ?
For technical support, including 74HC138D/AUJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC138D/AUJ requirements.
6.How does Aetrix verify that 74HC138D/AUJ is sourced from the original manufacturer or authorized distributors?
All 74HC138D/AUJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC138D/AUJ meets industry standards.
7.What is the process for return or replacement of 74HC138D/AUJ?
All 74HC138D/AUJ units undergo pre-shipment inspection (PSI). If there is an issue with 74HC138D/AUJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC138D/AUJ part is unused and in its original packaging.
Return procedure for 74HC138D/AUJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HC138D/AUJ Tags
-
SN74HC138DR
Texas Instruments
-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage
-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments
-
74CBTLV3257GUX
Nexperia USA Inc.
-
74HC154BQ,118
Nexperia USA Inc.
-
P3S0200GMX
NXP USA Inc.
-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments
-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments
-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
