NXP Semiconductors 74HC147D,652

Overview

74HC147D,652 from NXP Semiconductors (formerly Philips) is a 10-to-4 line priority encoder IC that converts nine active-LOW decimal inputs (A0–A8) into four active-LOW BCD outputs (Y0–Y3), with A8 assigned highest priority. It operates at 2–6 V supply, delivers 15 ns typical propagation delay at 5 V, and supports industrial temperature range (−40 °C to +125 °C). It is used in keyboard encoding and switch matrix decoding applications.

For engineers reviewing the 74HC147D,652 datasheet, 74HC147D,652 pinout, 74HC147D,652 application, or 74HC147D,652 equivalent, key selection considerations include active-LOW input/output logic polarity, priority encoding behavior under multiple simultaneous inputs, BCD output compatibility with downstream decoders, and CMOS-level DC/AC specifications across voltage and temperature ranges.

Technical Context

The 74HC147D,652 implements priority encoding using Si-gate CMOS technology, with all nine data inputs (A0–A8) and four outputs (Y0–Y3) asserted LOW. Input A8 has highest priority; when multiple inputs are LOW, only the highest-numbered active input determines the output code. The "zero" code (all outputs HIGH) is generated only when all inputs are HIGH.

It is pin-compatible with LSTTL and complies with JEDEC standard No. 7A. Propagation delay varies with supply voltage (2.0 V to 6.0 V) and load capacitance (15 pF or 50 pF), and transition times are specified separately for HC and HCT variants - this part is the HC version, optimized for CMOS input thresholds.

Key Specifications

Pinout & Package

74HC147D,652 is supplied in a 16-pin SO16 (Small Outline) package per JEDEC MS-012, with body width 3.9 mm and lead pitch 1.27 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar priority encoder applications.

Compared with SN74LS147N and 74HCT147D,653, the 74HC147D,652 offers lowest static power and widest supply range but requires careful attention to input voltage thresholds in mixed-logic systems - its CMOS inputs demand ≥3.5 V for reliable HIGH recognition at 5 V.

Availability

74HC147D,652 is available at Aetrix Electronics and suitable for industrial control panels, medical device keypads, and automotive diagnostic interfaces requiring stable component supply over extended product lifecycles.

Supply support for 74HC147D,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, delivering secure connectivity solutions for automotive, industrial, and IoT applications.

The 74HC147D,652 belongs to NXP's legacy 74HC logic family - designed for robust, low-power digital interfacing in systems requiring TTL-compatible functionality with CMOS efficiency and wide voltage operation.

FAQ

What is the logic polarity of inputs and outputs on the 74HC147D,652?

The 74HC147D,652 features active-LOW inputs (A0–A8) and active-LOW outputs (Y0–Y3). All nine inputs must be HIGH to generate the "zero" code (Y0–Y3 all HIGH). Any LOW input triggers encoding, with A8 having highest priority. This polarity is fixed and cannot be inverted internally - external inverters are required for active-HIGH signaling.

Does the 74HC147D,652 require external pull-up resistors on its outputs?

Yes, the 74HC147D,652 outputs are open-drain compatible only in functional behavior - they are push-pull but actively drive LOW and float HIGH. To ensure defined HIGH levels and noise immunity, 4.7 kΩ pull-up resistors to VCC are recommended on Y0–Y3, especially in noisy industrial environments or long trace runs.

Can the 74HC147D,652 operate at 3.3 V supply voltage?

Yes, the 74HC147D,652 is fully specified from 2.0 V to 6.0 V, including 3.3 V. At 3.3 V, propagation delay increases to ~22 ns (typical), and output drive strength decreases proportionally. Its CMOS input thresholds scale with VCC, ensuring reliable switching with 3.3 V logic families without level translation.

How does the 74HC147D,652 handle multiple simultaneous active inputs?

The 74HC147D,652 resolves multiple simultaneous LOW inputs using hardwired priority: A8 > A7 > … > A0. Only the highest-numbered active input determines the output code - lower-priority inputs are ignored. This behavior is implemented in silicon and requires no external arbitration or clocking.

Is the 74HC147D,652 pin-compatible with the 74LS147?

Yes, the 74HC147D,652 is pin-compatible with the 74LS147 and other 74xx147 variants in the 16-pin DIP and SO packages. Pin functions (A0–A8, Y0–Y3, VCC, GND, n.c.) match exactly. However, electrical characteristics differ - the 74HC147D,652 draws less current and operates over wider voltage/temperature ranges than the bipolar 74LS147.