NXP Semiconductors 74HC147DB,118

Overview

74HC147DB,118 from Nexperia (formerly Philips Semiconductors) is a 10-to-4 line priority encoder IC that converts nine active-LOW decimal inputs (A0–A8) into four active-LOW BCD outputs (Y0–Y3), with A8 assigned highest priority and implicit "zero" encoding when all inputs are HIGH; operates at 5 V supply, 15 ns typical propagation delay, and supports industrial temperature range (−40 °C to +125 °C); used in keyboard encoders and switch matrix interfaces.

For engineers reviewing the 74HC147DB,118 datasheet, 74HC147DB,118 pinout, 74HC147DB,118 application, or 74HC147DB,118 equivalent, key selection considerations include active-LOW input/output logic polarity, priority encoding behavior under multiple simultaneous inputs, BCD output compatibility with downstream decoders, and SO16 package footprint constraints for PCB layout.

Technical Context

The 74HC147DB,118 implements combinational priority encoding using Si-gate CMOS technology, with fixed input priority order (A8 > A7 > … > A0) and active-LOW signal assertion on both inputs and outputs. It requires no external clock or control signals and performs encoding in a single logic stage.

Its functional behavior relies on implied "zero" encoding-when all nine inputs are HIGH, all four outputs go HIGH to represent decimal 0-distinguishing it from non-priority or non-zero-encoding encoders. The device complies with JEDEC standard No. 7A and is TTL-input compatible in HCT variants, though this specific part is HC-grade.

Key Specifications

Pinout & Package

74HC147DB,118 is supplied in a 16-pin small outline (SO) package (SO16), body width 3.9 mm, pitch 1.27 mm, with gull-wing leads and moisture sensitivity level (MSL) 1 per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar priority encoder applications.

Compared with SN74LS147N and 74HCT147PW,118, the 74HC147DB,118 offers lowest static power and widest supply range but requires verified CMOS-compatible input levels; the HCT variant eases interface design where TTL thresholds are needed, while the LS version suits purely legacy TTL ecosystems despite higher dissipation.

Availability

74HC147DB,118 is available at Aetrix Electronics and suitable for industrial control panels, automotive diagnostic interfaces, and legacy system upgrades requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for 74HC147DB,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, analog, and discrete components, spun off from Philips in 2017 and headquartered in Nijmegen, Netherlands.

The 74HC147DB,118 belongs to Nexperia's 74HC logic family-designed for low-power, high-noise-immunity digital interfacing in industrial, automotive, and consumer equipment where robustness and long-term supply stability are critical.

FAQ

What is the logic polarity of inputs and outputs on the 74HC147DB,118?

The 74HC147DB,118 uses active-LOW logic on all nine inputs (A0–A8) and all four outputs (Y0–Y3). An asserted input is LOW; the encoded BCD result appears as active-LOW outputs. For example, input A3 LOW yields Y1 and Y0 LOW (0011 BCD = decimal 3, inverted). This polarity simplifies direct connection to grounded switches and open-collector drivers without inversion logic.

How does the 74HC147DB,118 handle the "zero" input condition?

The 74HC147DB,118 encodes "zero" implicitly when all nine inputs (A0–A8) are HIGH-causing all four outputs (Y0–Y3) to go HIGH. This eliminates the need for a dedicated "0" input line. The device does not require an external "zero" signal; the condition is detected internally and mapped deterministically to the all-HIGH output state, matching standard BCD zero representation when inverted externally if needed.

Is the 74HC147DB,118 pin compatible with the 74HCT147 series?

Yes, the 74HC147DB,118 is pin compatible with the 74HCT147 series-including 74HCT147PW,118-in the same SO16 package. Both share identical pin numbering, terminal functions, and physical footprint. However, the HC variant uses CMOS input thresholds (VIH ≈ 3.5 V at 5 V), while HCT uses TTL-compatible thresholds (VIH = 2.0 V min), so voltage-level compatibility must be verified per application.

What is the maximum recommended capacitive load for 74HC147DB,118 outputs?

The 74HC147DB,118 is characterized with CL = 15 pF for propagation delay (15 ns typ) and CL = 50 pF for AC performance (max tPD = 48 ns at VCC = 6.0 V). Driving loads beyond 50 pF may increase propagation delay nonlinearly and risk output transition time violations. For loads >50 pF, add a buffer stage or reduce trace length and capacitance-never exceed the absolute maximum output current rating (±25 mA per pin).

Does the 74HC147DB,118 require a pull-up or pull-down network on unused inputs?

Unused inputs on the 74HC147DB,118 must be tied HIGH (to VCC) via direct connection or pull-up resistor (≤10 kΩ). Leaving inputs floating risks metastability, increased ICC, and erroneous encoding due to noise-induced LOW transitions. Since all inputs are active LOW, a floating pin may be interpreted as asserted, causing unintended output changes. GND connections are prohibited on unused inputs unless intentionally asserting them.