NXP Semiconductors 74HC164DB,112

Overview

74HC164DB,112 from Nexperia is an 8-bit serial-in/parallel-out CMOS shift register with dual gated serial inputs (DSA and DSB), eight buffered parallel outputs (Q0–Q7), asynchronous master reset (MR), and edge-triggered clock (CP) operating on LOW-to-HIGH transitions. It supports 2.0 V to 6.0 V supply, delivers <8 μA ICC at 6 V/25 °C, and operates from –40 °C to +125 °C - used in LED matrix drivers, I/O expansion for microcontrollers, and serial-to-parallel data conversion in industrial control panels.

For engineers reviewing the 74HC164DB,112 datasheet, 74HC164DB,112 pinout, 74HC164DB,112 application, or 74HC164DB,112 equivalent, this page provides verified functional behavior, SO14 package mapping, timing-critical setup/hold values (tsu = 12 ns, th = +4 ns at VCC = 4.5 V), propagation delays (tpd = 15 ns typ), and direct substitution guidance against 74HCT164DB and SN74HC164N.

Technical Context

The device implements an 8-stage D-type flip-flop chain with synchronous serial loading and asynchronous reset. Data enters via either DSA or DSB, with the other acting as an active-HIGH enable - enabling flexible serial data routing without external gating logic. The MR input forces all Q outputs LOW independently of CP or data inputs.

Its CMOS architecture ensures high noise immunity (typ. 45 % VCC), rail-to-rail output swing (VOH ≥ 4.4 V, VOL ≤ 0.26 V at IO = ±4 mA, VCC = 4.5 V), and input clamp diodes supporting overvoltage-tolerant interfacing with current-limiting resistors.

Key Specifications

Pinout & Package

74HC164DB,112 uses the SO14 (SOT108-1) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads. Pin 1 index located at top-left corner with notch or dot marking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 8-bit serial-in/parallel-out shift register applications.

Compared with 74HC164DB,112, the 74HCT164DB,112 offers superior TTL input compatibility at minor power cost, while SN74HC164N trades surface-mount reliability for mechanical robustness and ease of manual assembly - selection depends on interface voltage family and assembly method.

Availability

74HC164DB,112 is available at Aetrix Electronics and suitable for LED display drivers, microcontroller I/O expansion, industrial serial bus interfaces, and automated test equipment requiring stable component supply across extended temperature ranges.

Supply support for 74HC164DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions with emphasis on efficiency, reliability, and sustainability - headquartered in Nijmegen, Netherlands.

The 74HC164 belongs to Nexperia's standard logic portfolio, designed specifically for robust serial-to-parallel data conversion in industrial automation, building controls, and consumer electronics where wide VCC range and high noise immunity are essential.

FAQ

What is the maximum clock frequency supported by 74HC164DB,112?

The 74HC164DB,112 achieves up to 85 MHz maximum clock frequency at VCC = 6.0 V and CL = 15 pF, per Table 7 of the official Nexperia datasheet Rev. 11. At 4.5 V and 50 pF load, typical propagation delay is 15 ns, yielding ~67 MHz practical limit. Performance degrades linearly below 4.5 V due to increased tpd.

Can DSA and DSB be used simultaneously for data input?

No - DSA and DSB are logically OR'd internally; only one may be driven LOW while the other is held HIGH to enable data entry. Driving both LOW holds the register, and driving both HIGH results in no shift action. This gating behavior is defined in Table 3 (Function Table) and Fig. 3 (Logic Diagram).

Is the MR (master reset) pin synchronous or asynchronous?

The MR pin is asynchronous and active LOW: asserting MR immediately forces Q0–Q7 to LOW regardless of CP state or timing. This behavior is confirmed in Section 1 (General description) and Table 3, where "Reset (clear)" mode shows Q outputs = L for any CP/DSA/DSB state when MR = L.

Does 74HC164DB,112 support 3.3 V operation?

Yes - the 74HC164DB,112 is fully specified from 2.0 V to 6.0 V, including 3.3 V nominal supply. At VCC = 3.3 V, VIH = 2.31 V min and VIL = 1.09 V max (interpolated from Table 6), and tpd ≈ 22 ns (extrapolated from 2.0 V/4.5 V data), ensuring reliable operation with modern 3.3 V MCUs and FPGAs.