Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

NXP Semiconductors 74HC243D,112

Name: 74HC243D,112
Brand: NXP Semiconductors
SKU: 74HC243D,112
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 74HC243D,112

Manufacturer:: NXP Semiconductors

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 14-SOIC (0.154", 3.90mm Width)

Datasheet:: 74HC243D,112.pdf

Description:: IC TXRX NON-INVERT 6V 14SO

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,846

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

74HC243D,112 from NXP Semiconductors (formerly Philips) is a high-speed CMOS quad bus transceiver with non-inverting 3-state outputs in both directions, pin-compatible with LSTTL, specified per JEDEC 7A, and rated for −40 °C to +125 °C operation. It enables asynchronous bidirectional data transfer across two 4-bit buses-e.g., between microcontroller address/data buses and peripheral memory or I/O subsystems.

For engineers reviewing the 74HC243D,112 datasheet, 74HC243D,112 pinout, 74HC243D,112 application, or 74HC243D,112 equivalent, key selection criteria include propagation delay (6 ns typ. at 5 V/15 pF), 3-state enable/disable timing (14–28 ns), supply voltage range (2.0–6.0 V), input/output capacitance (10 pF), and SO14 package compatibility with industrial temperature requirements.

Technical Context

The 74HC243D,112 implements dual independent 4-bit bidirectional data paths controlled by separate active-low output enable inputs (OEA and OEB), allowing full bus isolation when either control signal is HIGH. Its non-inverting architecture ensures true-level data transmission without polarity inversion during send or receive operations.

Each transceiver channel supports ±35 mA output drive, operates with static input leakage ≤±1.0 µA at 6 V, and maintains 3-state OFF-state current ≤±10.0 µA over −40 °C to +125 °C-enabling reliable bus contention management in mixed-voltage or hot-swap-capable systems.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	2.0 V to 6.0 V - supports direct interface with 3.3 V and 5 V logic domains without level shifting
Propagation Delay (An↔Bn)	6 ns typical at VCC = 5 V, CL = 15 pF - enables sub-100 MHz synchronous bus handshaking
3-State Enable Time (OEA/OEB)	14 ns typical at VCC = 6 V - ensures fast bus arbitration and low-latency direction switching
Output Drive Capability	±35 mA per pin - sufficient to drive 50 pF loads with <15 ns transition time at 6 V
Input/Output Capacitance	10 pF - minimizes capacitive loading on shared bus lines and preserves signal integrity
Operating Temperature	−40 °C to +125 °C - qualified for under-hood automotive, industrial PLC, and telecom infrastructure use
ESD Protection	HBM >2000 V, MM >200 V - meets IEC 61000-4-2 Level 2 for board-level robustness

Pinout & Package

74HC243D,112 is housed in a plastic small outline package (SO14), 14-lead, 3.9 mm body width (SOT108-1), with standard 1.27 mm pitch and gull-wing leads suitable for reflow soldering.

Pin/Terminal	Circuit Role	Design Meaning
1 (OEA)	Active-low output enable A	Controls 3-state output drivers for A0–A3; HIGH disables all A-side outputs
2 (n.c.)	No connection	Internally unconnected; must remain floating or tied to GND/VCC per layout best practice
3 (A0)	Data I/O port A0	Bidirectional 4-bit bus line; direction determined by OEA/OEB state
4 (A1)	Data I/O port A1	Same as A0; forms first 4-bit segment of transceiver path
5 (A2)	Data I/O port A2	Same as A0; supports parallel 4-line data exchange
6 (A3)	Data I/O port A3	Same as A0; completes A-side 4-bit port
7 (GND)	Ground reference	0 V return path for all internal logic and I/O circuits
8 (B3)	Data I/O port B3	Bidirectional 4-bit bus line; complements B0–B3 for full 4-bit path
9 (B2)	Data I/O port B2	Same as B3; forms second 4-bit segment of transceiver path
10 (B1)	Data I/O port B1	Same as B3; enables full-duplex 4-line communication
11 (B0)	Data I/O port B0	Same as B3; completes B-side 4-bit port
12 (n.c.)	No connection	Internally unconnected; no external connection required
13 (OEB)	Active-low output enable B	Controls 3-state output drivers for B0–B3; HIGH disables all B-side outputs
14 (VCC)	Positive supply	Primary power rail; decoupling capacitor (100 nF) recommended within 5 mm

Key Features

Feature	Design Value
Non-inverting 3-state outputs	Preserves signal polarity in both directions-critical for address/data bus mirroring without logic inversion overhead
Asynchronous 2-way bus communication	Enables independent read/write cycles on A and B buses without clock synchronization or handshake protocol
JEDEC 7A compliance	Guarantees interoperability with legacy LSTTL systems and standardized test methodology across supply chain
Industrial temperature range	−40 °C to +125 °C operation validated per Table 6-supports deployment in engine control units and base station radios
Low dynamic power dissipation	CPD = 26 pF enables µW-level standby power at low frequencies and predictable µW-to-mW scaling with bus activity

Applications

Industrial Bus Isolation	Microcontroller Peripherals Interface
Use Scenario: Isolating CAN or RS-485 transceiver data lines from a main system bus during fault conditions or firmware updates. IC Role / Device Role / Timing Role: Bidirectional 4-bit data bridge with independent OEA/OEB control enabling selective bus partitioning without interrupting other subsystems. Use Value: Prevents bus lock-up during peripheral reset; supports hot-swap capability with <28 ns disable time and <10 ns enable time at 6 V.	Use Scenario: Connecting an 8-bit microcontroller's lower address/data bus (AD0–AD3) to external EEPROM or LCD controller with shared bus topology. IC Role / Device Role / Timing Role: Non-inverting transceiver providing true-level data routing between MCU and peripheral, synchronized via dedicated OE signals. Use Value: Eliminates need for discrete inverters or additional glue logic; reduces PCB area and BOM count while maintaining <6 ns propagation delay.
Legacy System Bus Extension	Test Equipment Signal Routing
Use Scenario: Extending a vintage 8085-based system bus to add new I/O cards while preserving LSTTL compatibility and timing margins. IC Role / Device Role / Timing Role: Pin-compatible CMOS replacement for 74LS243, delivering identical functionality with lower power and wider voltage tolerance. Use Value: Enables drop-in upgrade path with no PCB redesign; supports 2.0–6.0 V supply versus 4.75–5.25 V for LS parts, easing power supply design.	Use Scenario: Dynamic signal path configuration in automated test equipment (ATE), where 4-bit control lines route between DUT interface and pattern generator. IC Role / Device Role / Timing Role: Reconfigurable bidirectional data switch controlled by FPGA GPIOs driving OEA/OEB, enabling real-time path selection. Use Value: Achieves <15 ns max propagation delay and <43 ns max disable time-meeting sub-20 ns setup/hold windows for high-speed digital pattern generation.

Industrial Bus Isolation

Microcontroller Peripherals Interface

Use Scenario: Isolating CAN or RS-485 transceiver data lines from a main system bus during fault conditions or firmware updates.

IC Role / Device Role / Timing Role: Bidirectional 4-bit data bridge with independent OEA/OEB control enabling selective bus partitioning without interrupting other subsystems.

Use Value: Prevents bus lock-up during peripheral reset; supports hot-swap capability with <28 ns disable time and <10 ns enable time at 6 V.

Use Scenario: Connecting an 8-bit microcontroller's lower address/data bus (AD0–AD3) to external EEPROM or LCD controller with shared bus topology.

IC Role / Device Role / Timing Role: Non-inverting transceiver providing true-level data routing between MCU and peripheral, synchronized via dedicated OE signals.

Use Value: Eliminates need for discrete inverters or additional glue logic; reduces PCB area and BOM count while maintaining <6 ns propagation delay.

Legacy System Bus Extension

Test Equipment Signal Routing

Use Scenario: Extending a vintage 8085-based system bus to add new I/O cards while preserving LSTTL compatibility and timing margins.

IC Role / Device Role / Timing Role: Pin-compatible CMOS replacement for 74LS243, delivering identical functionality with lower power and wider voltage tolerance.

Use Value: Enables drop-in upgrade path with no PCB redesign; supports 2.0–6.0 V supply versus 4.75–5.25 V for LS parts, easing power supply design.

Use Scenario: Dynamic signal path configuration in automated test equipment (ATE), where 4-bit control lines route between DUT interface and pattern generator.

IC Role / Device Role / Timing Role: Reconfigurable bidirectional data switch controlled by FPGA GPIOs driving OEA/OEB, enabling real-time path selection.

Use Value: Achieves <15 ns max propagation delay and <43 ns max disable time-meeting sub-20 ns setup/hold windows for high-speed digital pattern generation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad bus transceiver applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
74HC242D,653	Inverting outputs (A→B and B→A invert polarity); otherwise identical pinout, timing, and voltage specs	Requires complementary logic inversion in system design; unsuitable where true-level bus mirroring is mandatory	Select only if system-level inversion is already implemented or desired for noise immunity
SN74LVC243APWR	Lower VCC range (1.65–3.6 V); higher drive (±24 mA); different pinout (OEA/OEB on pins 1/13 same, but A/B order differs)	Not pin-compatible; requires PCB redesign; optimized for 3.3 V-only systems with tighter timing budgets	Choose for new 3.3 V designs needing lower voltage operation and faster 3.3 V transitions, not for drop-in replacement

Compared with 74HC243D,112, the 74HC242D,653 provides functional equivalence except for signal inversion-making it unsuitable where polarity preservation is critical-while the SN74LVC243APWR offers superior speed at 3.3 V but mandates layout changes due to non-identical pin mapping and voltage domain constraints.

Availability

74HC243D,112 is available at Aetrix Electronics and suitable for industrial automation, automotive ECU bus extension, and legacy system upgrades requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74HC243D,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors, formerly Philips Semiconductors, is a global leader in high-performance mixed-signal ICs, with core expertise in logic, interface, and automotive-grade components.

The 74HC243D,112 belongs to NXP's 74HC high-speed CMOS logic family, designed specifically for robust, low-power bidirectional bus interfacing in industrial, automotive, and computing applications demanding JEDEC-compliant timing and wide-temperature reliability.

FAQ

What is the maximum operating supply voltage for the 74HC243D,112?

The 74HC243D,112 supports a maximum supply voltage of +7.0 V per absolute maximum ratings (Table 5), but its recommended operating range is 2.0 V to 6.0 V (Table 6). Operation above 6.0 V risks exceeding dynamic power limits and degrading long-term reliability-even though the device may function temporarily at 7 V, sustained use beyond 6.0 V is not advised. The 74HC243D,112 is fully characterized and guaranteed across 2.0–6.0 V.

Does the 74HC243D,112 support hot-swapping between powered buses?

The 74HC243D,112 features robust bus-hold and high-impedance isolation: when OEA or OEB is HIGH, outputs enter 3-state mode with OFF-state current ≤±10.0 µA (Table 7, Tamb = −40 °C to +125 °C), and input leakage remains ≤±1.0 µA. This allows safe insertion/removal while adjacent buses remain live-provided VCC sequencing follows manufacturer guidelines and no voltage exceeds 7.0 V on any pin relative to GND. The 74HC243D,112 is commonly deployed in hot-swap backplane interfaces.

How does the 74HC243D,112 differ from the 74HC242D,653?

The 74HC243D,112 has non-inverting outputs (true-level transmission in both directions), whereas the 74HC242D,653 has inverting outputs. Both share identical pinout, supply range, temperature rating, propagation delay (6 ns typ.), and 3-state timing. The functional difference is strictly polarity: 74HC243D,112 passes A0–A3 → B0–B3 unchanged, while 74HC242D,653 inverts each bit. No other electrical or mechanical differences exist between the two devices.

Can the 74HC243D,112 be used with 3.3 V logic systems?

Yes-the 74HC243D,112 is fully specified down to 2.0 V and operates reliably at 3.3 V. At VCC = 3.3 V, VOH ≥ 3.1 V (IO = −20 µA) and VOL ≤ 0.2 V (IO = 6 mA), meeting 3.3 V LVTTL input thresholds. Propagation delay increases to ~12 ns (typ.) versus 6 ns at 5 V, but remains well within most 3.3 V system timing budgets. The 74HC243D,112 is widely used in mixed-voltage systems bridging 3.3 V peripherals to 5 V controllers.

What package type is used for the 74HC243D,112?

The 74HC243D,112 uses the SO14 plastic small outline package (SOT108-1), with 14 gull-wing leads, 1.27 mm pitch, and 3.9 mm body width. This surface-mount package is RoHS-compliant, reflow-solder compatible, and dimensionally identical to industry-standard SOIC-14 footprints-enabling direct placement on PCBs designed for generic 14-pin SOIC layouts. Pin 1 is marked by a notch or bevel on the package edge.

74HC243D,112 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: 74HC

Package/Case:: 14-SOIC (0.154", 3.90mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Logic Type:: Transceiver, Non-Inverting

Number of Elements:: 1

Number of Bits per Element:: 4

Input Type:: -

Output Type:: 3-State

Current - Output High, Low:: 7.8mA, 7.8mA

Voltage - Supply:: 2V ~ 6V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-SO

74HC243D,112 FAQ

1.How can I place an order for 74HC243D,112 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74HC243D,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74HC243D,112 reliable?

The price and inventory of 74HC243D,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC243D,112 is usually 5 days.

3.What payment methods are accepted for 74HC243D,112?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC243D,112 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 74HC243D,112?

74HC243D,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74HC243D,112 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74HC243D,112?

For technical support, including 74HC243D,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC243D,112 requirements.

6.How does Aetrix verify that 74HC243D,112 is sourced from the original manufacturer or authorized distributors?

All 74HC243D,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC243D,112 meets industry standards.

7.What is the process for return or replacement of 74HC243D,112?

All 74HC243D,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC243D,112, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74HC243D,112 part is unused and in its original packaging.

Return procedure for 74HC243D,112:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…