NXP Semiconductors 74HC367DB,112
- Part No.:
- 74HC367DB,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74HC367DB,112.pdf
- Description:
- IC BUFF DVR TRI-ST HEX 16SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,496
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HC367DB,112 from Nexperia is a hex non-inverting buffer/line driver with 3-state outputs, designed for bus interface and data routing in digital systems. It operates across 2.0 V to 6.0 V supply, delivers propagation delay as low as 8 ns at VCC = 6.0 V, supports -40 °C to +125 °C ambient range, and features TTL-compatible input thresholds when used as 74HCT367 variant - deployed in industrial control backplanes and microcontroller I/O expansion.
For engineers reviewing the 74HC367DB,112 datasheet, 74HC367DB,112 pinout, 74HC367DB,112 application, or 74HC367DB,112 equivalent, key selection criteria include 3-state output timing (enable/disable times ≤38 ns), CMOS-level input compatibility, SO16 package thermal derating (12.4 mW/K above 110 °C), and static drive capability (±35 mA per output).
Technical Context
This device implements six independent non-inverting buffers, each with active-low 3-state enable control (1OE, 2OE) allowing bidirectional bus management. All inputs include clamp diodes enabling safe interfacing to voltages exceeding VCC via current-limiting resistors.
It conforms to JEDEC JESD7A (2.0 V–6.0 V) and JESD8C (2.7 V–3.6 V) standards, supports HBM ESD >2000 V and CDM >1000 V, and guarantees latch-up immunity >100 mA per JESD78 Class II Level B - ensuring robust operation in noisy industrial environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - enables direct interface with 3.3 V and 5 V logic domains without level shifters |
| Propagation Delay (tpd) | 8 ns max at VCC = 6.0 V, CL = 50 pF - ensures sub-10 ns timing margin for 50 MHz bus clocking |
| 3-State Enable Time (ten) | 13 ns max at VCC = 6.0 V - critical for fast bus arbitration and dynamic load switching |
| Output Drive Current | ±35 mA per output - sufficient to drive 50 pF loads with <15 ns transition time (tt) |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive modules and industrial PLCs |
| Input Clamp Diodes | Integrated - permits safe overvoltage input protection up to VCC + 0.5 V using external series resistors |
| Power Dissipation Capacitance | 30 pF per buffer - enables accurate dynamic power estimation (PD = CPD × VCC² × fi × N) |
Pinout & Package
74HC367DB,112 is packaged in SO16 (SOT109-1): plastic small outline, 16-pin, 3.9 mm body width, 1.27 mm pitch, with standard JEDEC MS-012 footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low 3-state enable inputs - each controls three outputs; LOW enables, HIGH forces high-impedance |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Buffer input pins - CMOS-level compatible; clamp diodes allow overvoltage tolerance |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Non-inverting buffered outputs - 3-state capable; drive ±35 mA into resistive or capacitive loads |
| 8 | GND | Ground reference - must be connected to system 0 V plane with low-inductance path for noise immunity |
| 16 | VCC | Positive supply - decoupling capacitor (100 nF ceramic) required within 5 mm of pin for stable operation |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 2.0 V–6.0 V operation - eliminates need for separate voltage rails in mixed-supply systems |
| 3-state bus control | Dual enable inputs (1OE/2OE) partition outputs into two groups of three - simplifies multi-master bus arbitration |
| High noise immunity | CMOS input structure with >40 % VCC noise margin at 5 V - resists EFT and radiated interference |
| Latch-up robustness | Exceeds 100 mA per JESD78 Class II Level B - prevents destructive latch-up during transient overcurrent |
| ESD protection | HBM >2000 V, CDM >1000 V - meets IEC 61000-4-2 Level 4 for system-level ESD resilience |
Applications
| Industrial PLC Backplane Interface | Microcontroller I/O Expansion |
|---|---|
Use Scenario: Isolating and buffering address/data lines between CPU module and modular I/O racks in programmable logic controllers. IC Role / Device Role / Timing Role: Hex buffer provides level translation and fan-out amplification while 3-state outputs prevent bus contention during rack hot-swap. Use Value: Enables deterministic 8 ns propagation delay and 13 ns enable timing - meeting 20 MHz backplane timing budgets with margin. |
Use Scenario: Expanding GPIO count of ARM Cortex-M microcontrollers for sensor array readout and actuator control in edge devices. IC Role / Device Role / Timing Role: Acts as bi-directional bus driver with independent enable control per group, supporting time-multiplexed peripheral access. Use Value: ±35 mA drive strength allows direct connection to LED indicators and relay drivers without external transistors. |
| Automotive Body Control Module | Test Equipment Signal Routing |
Use Scenario: Driving LIN bus transceiver enable signals and multiplexing diagnostic lines in vehicle body control units. IC Role / Device Role / Timing Role: Provides noise-immune signal conditioning and 3-state isolation between MCU and external CAN/LIN PHY layers. Use Value: -40 °C to +125 °C qualification and integrated clamp diodes support direct integration near engine bay electronics. |
Use Scenario: Switching test vectors between multiple DUTs on automated test fixtures with minimal crosstalk and skew. IC Role / Device Role / Timing Role: Functions as precision-controlled signal gate with matched propagation delays (<5 ns skew between channels). Use Value: 30 pF CPD per buffer enables accurate dynamic power modeling for thermal design of densely packed ATE boards. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HC367D,112 | Same die, SO16 package without 'B' suffix - identical electrical specs and pinout | No functional difference; 'B' denotes tape-and-reel packaging variant per Nexperia ordering convention | Select 74HC367D,112 only if bulk or tube packaging is required; otherwise 74HC367DB,112 preferred for SMT automation. |
| SN74LVC1G34DBVR | Single-channel LVC variant - 1.65 V–5.5 V supply, 3.7 ns tpd, no 3-state output | Not a drop-in replacement - requires six discrete units and external enable logic for equivalent functionality | Choose only for ultra-low-power, space-constrained designs where full hex functionality is unnecessary. |
Compared with 74HC367DB,112, the 74HC367D,112 offers identical performance in alternate packaging, while SN74LVC1G34DBVR trades integration density and 3-state control for lower voltage operation and single-gate flexibility - making it unsuitable for bus interface but viable for point-to-point signal conditioning.
Availability
74HC367DB,112 is available at Aetrix Electronics and suitable for industrial control backplanes, microcontroller I/O expansion, automotive body control modules, and automated test equipment requiring stable component supply across extended temperature ranges.
Supply support for 74HC367DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and MOSFET solutions with emphasis on reliability and manufacturability.
The 74HC367DB,112 belongs to Nexperia's HC logic family, engineered for low-power, high-noise-immunity digital interfacing in industrial and automotive applications where robustness and wide supply range are mandatory.
FAQ
What is the maximum operating supply voltage for 74HC367DB,112?
The absolute maximum supply voltage for 74HC367DB,112 is +7.0 V, but the recommended operating range is 2.0 V to 6.0 V per datasheet Table 5. Operation above 6.0 V risks permanent damage and violates JEDEC JESD7A compliance - sustained use at 7.0 V is prohibited even for transient conditions.
Does 74HC367DB,112 support TTL-level inputs?
No - 74HC367DB,112 is the CMOS-input variant; its input thresholds scale with VCC (VIH ≥ 0.7×VCC, VIL ≤ 0.3×VCC). For TTL compatibility, use 74HCT367DB,112 instead, which specifies VIH = 2.0 V min and VIL = 0.8 V max at VCC = 4.5 V–5.5 V.
How many output enable inputs does 74HC367DB,112 have, and how are they assigned?
74HC367DB,112 has two active-low output enable inputs: 1OE (pin 1) controls outputs 1Y, 2Y, and 3Y; 2OE (pin 15) controls outputs 4Y, 5Y, and 6Y. This dual-enable architecture allows independent gating of two 3-bit bus segments - essential for multi-master arbitration schemes.
What is the thermal derating behavior of 74HC367DB,112 in SO16 package?
In the SO16 (SOT109-1) package, 74HC367DB,112 total power dissipation (Ptot) derates linearly at 12.4 mW/K above +110 °C ambient. At +125 °C, maximum allowable Ptot drops to 313 mW from the rated 500 mW - requiring careful thermal design in sealed enclosures or high-ambient environments.
Can 74HC367DB,112 be used in automotive applications?
Yes - 74HC367DB,112 is qualified for -40 °C to +125 °C operation and meets JESD78 latch-up and JEDEC ESD requirements, making it suitable for non-safety-critical automotive applications like body control modules and infotainment interfaces. It is not AEC-Q100 qualified, so safety-critical systems require additional validation.
74HC367DB,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HC
- Package/Case:
- 16-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SSOP
74HC367DB,112 FAQ
1.How can I place an order for 74HC367DB,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC367DB,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC367DB,112 reliable?
The price and inventory of 74HC367DB,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC367DB,112 is usually 5 days.
3.What payment methods are accepted for 74HC367DB,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC367DB,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC367DB,112?
74HC367DB,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC367DB,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC367DB,112?
For technical support, including 74HC367DB,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC367DB,112 requirements.
6.How does Aetrix verify that 74HC367DB,112 is sourced from the original manufacturer or authorized distributors?
All 74HC367DB,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC367DB,112 meets industry standards.
7.What is the process for return or replacement of 74HC367DB,112?
All 74HC367DB,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC367DB,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC367DB,112 part is unused and in its original packaging.
Return procedure for 74HC367DB,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HC367DB,112 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

