NXP Semiconductors 74HC367PW,112
- Part No.:
- 74HC367PW,112
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74HC367PW,112.pdf
- Description:
- IC BUFFER NON-INVERT 6V 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74HC367PW,112 from Nexperia is a hex non-inverting 3-state buffer/line driver in TSSOP16 package, operating from 2.0 V to 6.0 V supply, with CMOS-level inputs, propagation delay as low as 8 ns at VCC = 6.0 V, and guaranteed operation from −40 °C to +125 °C. It enables bidirectional bus interfacing in industrial control backplanes and microcontroller I/O expansion systems.
For engineers reviewing the 74HC367PW,112 datasheet, 74HC367PW,112 pinout, 74HC367PW,112 application, or 74HC367PW,112 equivalent, key selection criteria include 3-state output timing (enable/disable times ≤ 38 ns), input clamp diode support for overvoltage-tolerant interfacing, and thermal derating behavior (8.5 mW/K above 91 °C) in the TSSOP16 footprint.
Technical Context
This device implements six independent non-inverting buffers, each with active-low 3-state enable control (1OE, 2OE). Outputs enter high-impedance OFF-state when respective OE is HIGH, allowing shared-bus contention-free operation. Input clamp diodes permit safe interface to signals exceeding VCC when used with current-limiting resistors.
Logic behavior follows standard TTL-compatible truth table: output equals input when OE is LOW; output is Z (high-Z) when OE is HIGH. Static drive capability includes VOH ≥ 3.98 V at IO = −6.0 mA (VCC = 4.5 V) and VOL ≤ 0.26 V at IO = 6.0 mA, ensuring robust noise margins across temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 2.0 V to 6.0 V - supports mixed-voltage system interfacing including 3.3 V and 5 V logic domains |
| Propagation delay (nA→nY) | 8 ns (typ) at VCC = 6.0 V, CL = 50 pF - enables sub-100 MHz bus timing in synchronous data paths |
| Enable/disable time | 13–38 ns (max) - ensures fast bus arbitration and minimizes glitch windows during state transitions |
| Output drive strength | ±6.0 mA (min) at VCC = 4.5 V - sufficient to drive 50 pF loads with <10 ns transition times |
| Input clamp current | ±20 mA - allows external resistor-limited interface to voltages up to VCC + 0.5 V or below GND − 0.5 V |
| Operating temperature | −40 °C to +125 °C - qualified for extended industrial and under-hood automotive-adjacent environments |
| Power dissipation capacitance | 30 pF per buffer - enables accurate dynamic power estimation using PD = CPD × VCC² × fi × N |
Pinout & Package
TSSOP16 plastic thin shrink small outline package (SOT403-1), 16-pin, body width 4.4 mm, lead pitch 0.65 mm, rated for reflow soldering per JEDEC J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low 3-state enable inputs - each controls three outputs (1OE → 1Y/2Y/3Y; 2OE → 4Y/5Y/6Y) |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Buffer input terminals - accept CMOS-level signals; include internal clamp diodes to VCC and GND |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Non-inverting buffered outputs - present high-Z state when corresponding OE is HIGH |
| 8 | GND | Ground reference - must be connected to system 0 V plane with low-inductance path for noise immunity |
| 16 | VCC | Positive supply - decoupling capacitor (100 nF ceramic) required within 5 mm of this pin |
Key Features
| Feature | Design Value |
|---|---|
| Wide supply voltage range | 2.0 V to 6.0 V - eliminates need for level shifters when interfacing 3.3 V MCUs to 5 V peripherals |
| CMOS-level input compatibility | VIH ≥ 1.5 V (VCC = 2.0 V), VIL ≤ 0.5 V - ensures reliable recognition of low-voltage logic thresholds |
| High noise immunity | Typical HNM = 1.2 V at VCC = 4.5 V - suppresses false triggering from EMI-coupled transients on PCB traces |
| ESD protection | HBM > 2000 V, CDM > 1000 V - reduces risk of field failure during handling and board assembly |
| Latch-up immunity | Exceeds 100 mA per JESD78 Class II Level B - prevents destructive parasitic SCR activation under transient overstress |
Applications
| Industrial PLC Backplane Interface | Microcontroller GPIO Expansion |
|---|---|
Use Scenario: Isolating and buffering address/data lines between CPU module and modular I/O racks in programmable logic controllers. IC Role / Device Role / Timing Role: Hex buffer provides fan-out amplification and 3-state isolation to prevent bus contention during rack hot-swap or module configuration changes. Use Value: Enable/disable timing ≤38 ns ensures deterministic bus release before next master cycle, eliminating arbitration glitches in multi-master backplanes. |
Use Scenario: Extending limited GPIO count of ARM Cortex-M0+ MCU to drive multiple LED indicators, relays, and sensor interface lines. IC Role / Device Role / Timing Role: Non-inverting line driver translates MCU logic levels to higher-current outputs while enabling software-controlled bus release via OE pins. Use Value: ±6 mA drive strength directly drives LEDs without external transistors; 3-state mode reduces standby current in sleep states. |
| Test Equipment Signal Routing | Legacy Bus Protocol Translation |
Use Scenario: Multiplexing digital stimulus signals from ATE pattern generator to DUT pins in automated test fixtures. IC Role / Device Role / Timing Role: 3-state buffer acts as signal gate, controlled by test sequencer to route one of six parallel channels to shared probe head. Use Value: Propagation delay variation <5 ns across all six channels ensures synchronized edge delivery critical for setup/hold compliance. |
Use Scenario: Adapting 3.3 V FPGA I/O banks to legacy 5 V parallel bus standards (e.g., ISA, PC/104) without level-shifter ICs. IC Role / Device Role / Timing Role: Voltage-tolerant input clamps allow direct connection to 5 V signals; output swing meets 5 V TTL VOH/VOL specs at 6 mA load. Use Value: Eliminates discrete resistor networks or dedicated level translators, reducing BOM count and layout area in space-constrained adapters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT367PW,112 | TTL-level inputs (VIH = 2.0 V min), identical pinout and timing | Better compatibility with legacy 5 V TTL sources; slightly higher ICC at VCC = 5 V | Select when driving from standard 5 V logic families without pull-ups |
| SN74LVC6T244RGYR | 3.3 V only (1.65–3.6 V), dual 3-bit configuration, different pin mapping | Lower power (ICC < 10 μA), but requires PCB redesign due to non-pin-compatible layout | Choose for new 3.3 V-only designs prioritizing ultra-low static current and smaller footprint |
Compared with 74HC367PW,112, the 74HCT367PW,112 offers superior TTL input compatibility at no layout cost, while the SN74LVC6T244RGYR delivers lower power and smaller size at the expense of voltage range and pinout continuity.
Availability
74HC367PW,112 is available at Aetrix Electronics and suitable for industrial PLC backplanes, microcontroller GPIO expansion, and automated test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74HC367PW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable components for automotive, industrial, mobile, and consumer electronics markets, with leadership in logic, power MOSFETs, and ESD protection.
The 74HC367 belongs to Nexperia's HC-series high-speed CMOS logic family, designed specifically for robust, low-power bus interfacing in noise-prone industrial control and instrumentation applications.
FAQ
Can 74HC367PW,112 operate reliably at 2.0 V supply?
Yes. The device is fully specified down to 2.0 V: VIH minimum is 1.5 V, VIL maximum is 0.5 V, and propagation delay remains ≤95 ns (max) at CL = 50 pF. Output drive meets ±4 mA at 2.0 V, supporting low-voltage battery-powered systems with adequate noise margin.
What is the thermal derating behavior of the TSSOP16 package?
The TSSOP16 (SOT403-1) package has a total power dissipation limit of 500 mW at TA ≤ 91 °C, derating linearly by 8.5 mW/K above that temperature. At 125 °C ambient, maximum allowable power drops to approximately 215 mW, requiring careful thermal design in enclosed enclosures.
How do the input clamp diodes affect system design?
The integrated clamp diodes allow safe interface to signals up to VCC + 0.5 V or down to GND − 0.5 V, provided external series resistors limit clamp current to ≤±20 mA. This enables direct connection to overvoltage sources (e.g., 12 V sensors) without discrete protection diodes.
Are 1OE and 2OE logically independent?
Yes. Pin 1 (1OE) controls outputs 1Y, 2Y, and 3Y; pin 15 (2OE) controls outputs 4Y, 5Y, and 6Y. Each OE operates independently, enabling partial bus gating - for example, holding 1Y–3Y active while releasing 4Y–6Y to high-Z for concurrent peripheral access.
74HC367PW,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HC
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
74HC367PW,112 FAQ
1.How can I place an order for 74HC367PW,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC367PW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC367PW,112 reliable?
The price and inventory of 74HC367PW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC367PW,112 is usually 5 days.
3.What payment methods are accepted for 74HC367PW,112?
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5.How can I obtain technical support or documentation for 74HC367PW,112?
For technical support, including 74HC367PW,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC367PW,112 requirements.
6.How does Aetrix verify that 74HC367PW,112 is sourced from the original manufacturer or authorized distributors?
All 74HC367PW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC367PW,112 meets industry standards.
7.What is the process for return or replacement of 74HC367PW,112?
All 74HC367PW,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC367PW,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC367PW,112 part is unused and in its original packaging.
Return procedure for 74HC367PW,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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