NXP Semiconductors 74HC368D,652
- Part No.:
- 74HC368D,652
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74HC368D,652.pdf
- Description:
- IC BUFFER INVERT 6V 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:140,212
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74HC368D,652 from Nexperia is a hex inverting 3-state buffer/line driver in SO16 package, operating from 2.0 V to 6.0 V, with CMOS-level inputs, propagation delay of 9 ns (VCC = 6.0 V), and ±35 mA output drive capability-used for bus interfacing and signal isolation in industrial control backplanes.
For engineers reviewing the 74HC368D,652 datasheet, 74HC368D,652 pinout, 74HC368D,652 application, or 74HC368D,652 equivalent, key selection criteria include input voltage compatibility (CMOS), 3-state enable timing (ten = 12 ns max at VCC = 6.0 V), thermal derating (12.4 mW/K above 110 °C), and SO16 footprint compatibility with legacy 74-series designs.
Technical Context
This device implements six independent inverting buffers, each with active-low 3-state output control via dedicated OE pins (1OE on Pin 1, 2OE on Pin 15). Its logic function follows standard TTL-compatible truth table: when OE is LOW, output = NOT(input); when OE is HIGH, output enters high-impedance state.
Designed for mixed-voltage system interfacing, it features input clamp diodes enabling safe operation with input voltages exceeding VCC, and meets JEDEC JESD7A (2.0–6.0 V) and JESD8C (2.7–3.6 V) standards. Latch-up immunity exceeds 100 mA per JESD78 Class II Level B.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 6.0 V - supports direct interface with 3.3 V and 5 V logic domains without level shifters. |
| Propagation Delay (nA→nY) | 9 ns (max) at VCC = 6.0 V - enables reliable operation in 50 MHz+ data buses with 15 pF load. |
| Output Drive Strength | ±35 mA - sufficient to drive multiple TTL loads or terminate short PCB traces without external buffering. |
| Input Thresholds (VCC = 4.5 V) | VIH = 3.15 V min, VIL = 1.35 V max - ensures robust noise margin (>1.3 V) in noisy industrial environments. |
| 3-State Enable Time (ten) | 12 ns (max) at VCC = 6.0 V - guarantees fast bus arbitration and minimizes contention windows in shared-data systems. |
| Operating Temperature | −40 °C to +125 °C - qualified for under-hood, motor control, and industrial PLC applications. |
| Power Dissipation (Ptot) | 500 mW (SO16) - derates linearly at 12.4 mW/K above 110 °C, supporting sustained operation in enclosed enclosures. |
Pinout & Package
74HC368D,652 uses the SOT109-1 (SO16) plastic small outline package: 16-pin, 3.9 mm body width, 1.27 mm pitch, gull-wing leads, JEDEC MS-012 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low 3-state enable inputs - simultaneous assertion disables all three outputs per group (1Y–3Y and 4Y–6Y). |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Inverting data inputs - each drives corresponding inverted output only when its OE is asserted. |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Inverting 3-state outputs - high-impedance when OE = HIGH; logic complement of A when OE = LOW. |
| 8 | GND | Ground reference - must be low-inductance connection to minimize switching noise coupling into logic paths. |
| 16 | VCC | Positive supply - requires local 100 nF ceramic decoupling within 5 mm of pin to suppress dynamic current spikes. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (2.0–6.0 V) | Enables single-part support across 3.3 V microcontroller I/O and legacy 5 V peripheral buses. |
| Input clamp diodes | Permits use of series current-limiting resistors for safe interfacing to voltages up to VCC + 0.5 V. |
| High noise immunity | Typical noise margin >1.3 V at VCC = 4.5 V ensures reliable operation in electrically noisy factory-floor environments. |
| JEDEC-compliant 3-state timing | ten/tdis ≤ 12/16 ns (VCC = 6.0 V) meets strict bus turnaround requirements in IEEE 1149.1 JTAG and parallel test interfaces. |
| ESD protection | HBM >2000 V and CDM >1000 V reduce field failure risk during manual handling and board assembly. |
Applications
| Industrial Backplane Bus Isolation | Microcontroller GPIO Expansion |
|---|---|
|
Use Scenario: Isolating multiple PLC I/O modules sharing a common 5 V data bus while preventing signal contention during hot-swap events. IC Role / Device Role / Timing Role: Inverting 3-state buffer providing direction-controlled signal gating and bus hold-off during module reconfiguration. Use Value: Enables deterministic bus arbitration with <12 ns enable time and eliminates need for discrete pull-up networks on shared lines. |
Use Scenario: Expanding limited GPIO count of an ARM Cortex-M4 MCU to drive 12-channel LED status array and 6-channel relay control bank. IC Role / Device Role / Timing Role: Hex inverting driver translating 3.3 V logic levels to 5 V-compatible outputs with simultaneous 3-state control per group. Use Value: Reduces BOM count by replacing six discrete inverters and six MOSFET drivers while maintaining layout symmetry and trace length matching. |
| Legacy TTL-to-CMOS Interface Bridge | Test Equipment Signal Conditioning |
|
Use Scenario: Interfacing vintage 74LS TTL logic circuits to modern low-power CMOS FPGAs in equipment refurbishment projects. IC Role / Device Role / Timing Role: Level-shifting inverting buffer with TTL-compatible input thresholds (74HCT variant) and CMOS output drive strength. Use Value: Eliminates need for external level translators; supports bidirectional signal flow via OE-controlled tristate on both sides of legacy bus. |
Use Scenario: Driving calibrated 50 Ω coaxial cables from FPGA I/O banks in automated test fixtures requiring precise edge control and impedance matching. IC Role / Device Role / Timing Role: Low-skew inverting line driver with 13 ns max transition time (tt) and 30 pF CPD per buffer for predictable dynamic loading. Use Value: Maintains signal integrity up to 35 MHz without external termination; enables synchronous multi-channel stimulus generation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex inverting 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74HCT368D,652 | TTL-compatible inputs (VIH = 2.0 V min), identical SO16 package and pinout. | Better suited for mixed 5 V TTL/CMOS systems where input noise immunity is secondary to legacy compatibility. | Select when interfacing with 74LS/74ALS families; avoid if system uses pure CMOS signaling with <2.0 V logic highs. |
| SN74LVC368APWR | 3.3 V only (1.65–3.6 V), lower VOH (2.7 V min @ 24 mA), smaller TSSOP16 package. | Optimized for battery-powered portable instruments; not pin-compatible due to different pin mapping and voltage domain. | Choose for space-constrained 3.3 V designs requiring lower static power (<1 μA ICC); requires PCB redesign. |
Compared with 74HC368D,652, the 74HCT368D,652 offers superior legacy TTL interoperability but reduced noise margin, while SN74LVC368APWR delivers lower voltage operation and footprint savings at the cost of full pin and voltage compatibility.
Availability
74HC368D,652 is available at Aetrix Electronics and suitable for industrial automation, test equipment design, and legacy system integration requiring stable component supply, long-term obsolescence management, and RoHS-compliant SO16 packaging.
Supply support for 74HC368D,652 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and discrete components for automotive, industrial, and consumer markets.
The 74HC368 belongs to Nexperia's industry-standard 74HC logic family, designed for robust, low-power digital interfacing in harsh environments where reliability and wide supply tolerance are critical.
FAQ
What is the maximum clock frequency supported by 74HC368D,652?
The 74HC368D,652 is not a clocked device-it has no internal clock and operates asynchronously. Its usable data rate depends on propagation delay (9 ns max at VCC = 6.0 V) and load capacitance. With 15 pF load, it reliably supports data edges up to ~35 MHz in point-to-point configurations, assuming proper PCB layout and termination.
Can 74HC368D,652 drive a 50 Ω transmission line directly?
No-its output impedance is not matched to 50 Ω, and driving such a load continuously risks exceeding ±35 mA absolute maximum rating. For 50 Ω lines, use a dedicated line driver (e.g., SN65LVDS1) or add series termination. The 74HC368D,652 is intended for bus loading (e.g., 10–50 pF) and short PCB trace fanout.
Is there a non-inverting version of this part?
Yes-the 74HC367D,652 is the functional complement: hex non-inverting 3-state buffer with identical SO16 package, pinout, and electrical specifications. It shares the same 1OE/2OE control architecture and operates across 2.0–6.0 V, enabling drop-in replacement where signal polarity must be preserved.
Does 74HC368D,652 require external pull-up resistors on its outputs?
No-outputs are actively driven HIGH or LOW when enabled, and enter true high-impedance (not floating) state when disabled. Pull-ups are unnecessary unless required by downstream logic (e.g., open-drain receivers). Adding them unnecessarily increases static power and slows disable transitions due to RC time constant.
74HC368D,652 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
74HC368D,652 FAQ
1.How can I place an order for 74HC368D,652 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC368D,652 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC368D,652 reliable?
The price and inventory of 74HC368D,652 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC368D,652 is usually 5 days.
3.What payment methods are accepted for 74HC368D,652?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC368D,652 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC368D,652?
74HC368D,652 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC368D,652 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC368D,652?
For technical support, including 74HC368D,652 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC368D,652 requirements.
6.How does Aetrix verify that 74HC368D,652 is sourced from the original manufacturer or authorized distributors?
All 74HC368D,652 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC368D,652 meets industry standards.
7.What is the process for return or replacement of 74HC368D,652?
All 74HC368D,652 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC368D,652, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC368D,652 part is unused and in its original packaging.
Return procedure for 74HC368D,652:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74HC368D,652 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

