NXP Semiconductors 74HC390DB,112

Overview

74HC390DB,112 from Nexperia is a dual 4-bit binary/decimal ripple counter IC with asynchronous reset, operating at 2V–6V supply, 80MHz max clock frequency, and TTL-compatible inputs. It implements two independent divide-by-2/divide-by-5 counter sections in one SO-16 package for clock division and frequency synthesis in digital timing circuits.

For engineers reviewing the 74HC390DB,112 datasheet, 74HC390DB,112 pinout, 74HC390DB,112 application, or 74HC390DB,112 equivalent, key selection factors include dual independent counter architecture, asynchronous reset behavior, propagation delay (typ. 15ns at 4.5V), and SO-16 thermal performance in synchronous logic systems.

Technical Context

The 74HC390DB,112 integrates two electrically isolated 4-bit counter blocks: Counter A (pins 1–2–3) provides ÷2 and ÷5 outputs; Counter B (pins 5–6–7) provides ÷2 and ÷5 outputs. Each section uses master-slave JK flip-flops with gated clock enable and direct asynchronous reset (active-low).

It operates in HC CMOS logic family with rail-to-rail output swing, input hysteresis for noise immunity, and guaranteed fan-out of 10 LS-TTL loads. Propagation delays are specified per stage (e.g., CP0→QA: 15ns typ. at VCC=4.5V, TA=25°C), supporting cascaded multi-stage counting without external synchronization.

Key Specifications

Pinout & Package

74HC390DB,112 is housed in a 16-pin small-outline (SO-16) package with 1.27 mm pitch, JEDEC MS-012AC compliant, suitable for surface-mount reflow assembly and automated optical inspection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual binary/decimal counter applications.

Compared with 74HC390DB,112, the HCT variant improves input compatibility with older TTL sources, while the SN74HC390N offers mechanical interchangeability in through-hole systems-neither alters the core dual-counter functionality or timing behavior.

Availability

74HC390DB,112 is available at Aetrix Electronics and suitable for digital timing, industrial control, legacy system repair, and test equipment requiring stable component supply and long-term sourcing continuity.

Supply support for 74HC390DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors, delivering high-performance, reliable discrete, logic, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74HC390DB,112 belongs to Nexperia's 74HC logic family, engineered for robustness in industrial-grade environments with extended temperature range (−40°C to +125°C) and stringent ESD protection (HBM >2kV).

FAQ

What is the maximum operating frequency of the 74HC390DB,112?

The 74HC390DB,112 supports a maximum clock frequency of 80 MHz at VCC = 4.5 V and TA = 25 °C. At VCC = 2.0 V, the maximum usable frequency drops to 20 MHz due to increased propagation delay. These values are measured at the CP0 and CP1 inputs under standard load conditions (CL = 50 pF).

Can Counter A and Counter B operate from independent clock sources?

Yes - CP0 and CP1 are fully isolated inputs. Counter A responds only to CP0 transitions, and Counter B responds only to CP1 transitions. No internal coupling exists between the clock domains, enabling true dual-clock operation for asynchronous timing generation or event counting.

Is the 74HC390DB,112 pin-compatible with the 74LS390?

Yes - the 74HC390DB,112 shares identical pin assignment, function mapping, and SO-16 package dimensions with the 74LS390. However, its HC logic thresholds and lower power consumption require verification of driving source compatibility and decoupling practices in mixed-technology designs.

Does the 74HC390DB,112 support synchronous reset?

No - reset is strictly asynchronous and active-low on MR0 and MR1. There is no clock-synchronized reset input or internal synchronizer. To achieve synchronous reset behavior, external logic (e.g., AND gate combining MR and clock) must be added at the board level.