NXP Semiconductors 74HC7046AD,118
- Part No.:
- 74HC7046AD,118
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74HC7046AD,118.pdf
- Description:
- IC PHASE LOCK LOOP 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:1,354
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Product details
Overview
74HC7046AD,118 from NXP Semiconductors is a high-speed CMOS phase-locked-loop (PLL) IC with integrated lock detector, VCO, and dual phase comparators (XOR and edge-triggered JK). It delivers 17 MHz typical VCO center frequency at 4.5 V, 50% VCOOUT duty factor (±1%), and operates across 2.0–6.0 V digital supply and 3.0–6.0 V VCO supply. It enables FM demodulation and data synchronization in communication receivers.
For engineers reviewing the 74HC7046AD,118 datasheet, 74HC7046AD,118 pinout, 74HC7046AD,118 application, or 74HC7046AD,118 equivalent, key selection criteria include VCO linearity (≤0.4% at 4.5 V), lock detector output behavior (active-HIGH LD at pin 1), PC1/PC2 comparator trade-offs (harmonic locking vs. frequency discrimination), and external R/C tuning ranges (R1/R2: 3–300 kΩ; C1: ≥40 pF).
Technical Context
The 74HC7046AD,118 implements a linear voltage-controlled oscillator using op-amp buffering to achieve minimal frequency drift and zero voltage offset at VCOIN. Its dual-phase comparator architecture supports both XOR-based (PC1) and edge-triggered JK-based (PC2) detection, enabling distinct loop dynamics: PC1 provides high noise immunity and harmonic locking capability, while PC2 delivers precise frequency/phase alignment with 3-state output and no static phase error.
VCO frequency is set by external R1/C1 (or R1+R2/C1), with center frequency tunable from 7–21 MHz depending on supply and component values. The DEMOUT pin (pin 10) replicates VCOIN voltage without threshold drop, simplifying low-pass filter design and supporting direct demodulator interfacing without level-shifting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCO center frequency | 17 MHz typical at VCC = 4.5 V, R1 = 3 kΩ, C1 = 40 pF - defines nominal PLL operating point for synthesis or demodulation |
| VCO duty factor | 50% ±1% at constant VCOIN - ensures symmetrical clock output for downstream logic or modulation accuracy |
| VCO linearity | 0.4% max at VCC = 4.5 V - guarantees predictable frequency vs. control voltage response for linear FM or V/f conversion |
| Lock detector output | Active-HIGH LD at pin 1 - provides unambiguous system-level lock status without external logic |
| Supply voltage range | Digital section: 2.0–6.0 V; VCO section: 3.0–6.0 V - allows mixed-supply designs and low-power standby via INH control |
| Phase comparator options | PC1 (XOR) and PC2 (edge-triggered JK) - selectable per application: PC1 for noise-tolerant tone decoding, PC2 for jitter-sensitive data recovery |
| Input sensitivity (AC-coupled) | 15 mVp-p at 1 MHz - enables direct connection to low-amplitude signal sources without preamplification |
Pinout & Package
74HC7046AD,118 is housed in a 16-pin SO16 (small outline) plastic package per JEDEC MS-012, with 1.27 mm pitch and body dimensions 10.0 × 4.4 × 1.45 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (LD) | Lock detector output | Open-drain HIGH when PLL is locked; requires pull-up for logic-level interface |
| 2 (PC1OUT) | Phase comparator 1 output | XOR result of SIGIN and COMPIN; feeds low-pass filter to VCOIN |
| 3 (COMPIN) | Comparator input | Reference signal path for both PC1 and PC2; accepts DC- or AC-coupled inputs |
| 4 (VCOOUT) | VCO output | 50% duty cycle square wave; directly drives COMPIN or external divider |
| 5 (INH) | VCO inhibit control | Active-HIGH disables VCO and DEMOUT to reduce standby current below 160 µA |
| 6 (C1A), 7 (C1B) | VCO capacitor terminals | Differential connection for timing capacitor C1; sets VCO frequency range with R1/R2 |
| 8 (GND) | Ground reference | Common return for digital, VCO, and demodulator sections |
| 9 (VCOIN) | VCO control input | Analog voltage input (1.1–4.9 V) that linearly controls VCO frequency |
| 10 (DEMOUT) | Demodulator output | Buffered replica of VCOIN voltage; eliminates threshold drop for accurate filtering |
| 11 (R1), 12 (R2) | VCO resistor terminals | Set VCO center frequency and offset; parallel R1||R2 > 2.7 kΩ required |
| 13 (PC2OUT) | Phase comparator 2 output | 3-state up/down control signal; enables precise frequency acquisition without ripple |
| 14 (SIGIN) | Signal input | Self-biasing amplifier input; handles large swings (DC-coupled) or small signals (AC-coupled) |
| 15 (CLD) | Lock detector capacitor | Connects to GND via CLD capacitor; value determines lock detection time constant |
| 16 (VCC) | Positive supply | Powers digital logic and VCO sections; decoupling near pin essential for stability |
Key Features
| Feature | Design Value |
|---|---|
| Dual phase comparators | Hardware-selectable XOR (PC1) for harmonic tolerance or edge-triggered JK (PC2) for zero-phase-error frequency locking |
| VCO-inhibit control | INH pin reduces standby power by disabling VCO and DEMOUT while preserving digital state |
| Linear VCO architecture | Op-amp buffered VCOIN input achieves ≤0.4% frequency linearity - critical for analog FM demodulation fidelity |
| DEMOUT voltage replication | Pin 10 outputs exact VCOIN voltage (no diode drop), eliminating calibration offsets in analog filter designs |
| Wide supply flexibility | Digital logic operates down to 2.0 V while VCO requires only 3.0 V - enables partial-power-down modes |
Applications
| FM Demodulation | Frequency Synthesis |
|---|---|
Use Scenario: Recovering audio from broadcast FM signals in portable radios or telemetry receivers. IC Role / Device Role / Timing Role: PLL acts as quadrature demodulator where VCO tracks carrier; DEMOUT voltage represents instantaneous frequency deviation. Use Value: 0.4% VCO linearity ensures <1% distortion in recovered audio; 15 mVp-p input sensitivity allows direct antenna coupling without LNA. | Use Scenario: Generating stable local oscillator frequencies for SDR transceivers or test equipment. IC Role / Device Role / Timing Role: 74HC7046AD,118 locks VCO to crystal reference via PC2, producing programmable multiples of base frequency. Use Value: Dual comparator support enables fast acquisition (PC2) and noise-immune hold (PC1); 17 MHz center frequency covers HF/VHF bands. |
| Tone Decoding | Data Synchronization |
Use Scenario: Detecting DTMF or selective calling tones in security systems or industrial controllers. IC Role / Device Role / Timing Role: Configured with narrowband loop filter, PLL locks to specific tone; LD output signals tone presence. Use Value: PC1's harmonic locking allows detection of 2nd/3rd harmonics, reducing need for multiple filters; CLD capacitor tunes lock response time. | Use Scenario: Recovering clock and data from asynchronous serial streams in legacy industrial networks. IC Role / Device Role / Timing Role: PLL extracts embedded clock from NRZ data; VCOOUT retimes incoming bits to eliminate jitter. Use Value: 50% ±1% VCOOUT duty factor ensures balanced setup/hold margins; 3-state PC2OUT minimizes ripple-induced bit errors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar phase-locked-loop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4046BE | CMOS-compatible but older 4000-series; lower max VCO frequency (1.2 MHz at 5 V), no DEMOUT pin, no lock detector | Lacks integrated lock status and precision demodulator output; requires external circuitry for FM demod or tone decode | Choose only for legacy 4000-series designs where 74HC speed and features are unnecessary |
| SN74LV4046A | Lower-voltage optimized (1.65–5.5 V); improved propagation delay (19 ns typ.); same pinout but no PC1/PC2 selection flexibility | Optimized for 3.3 V systems; lacks PC1's harmonic-locking capability and DEMOUT voltage replication | Select when operating strictly at 3.3 V with priority on speed over analog demodulation fidelity |
Compared with CD4046BE and SN74LV4046A, the 74HC7046AD,118 uniquely combines high-frequency VCO operation (17 MHz), dual comparator selection, and buffered DEMOUT for analog-centric applications like FM demodulation-features absent in both alternatives.
Availability
74HC7046AD,118 is available at Aetrix Electronics and suitable for FM demodulation, frequency synthesis, tone decoding, and data synchronization requiring stable component supply across industrial temperature ranges (−40 °C to +125 °C).
Supply support for 74HC7046AD,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications.
The 74HC7046AD,118 belongs to NXP's legacy 74HC/HCT logic family, designed specifically for analog-digital hybrid systems requiring integrated PLL functionality with robust noise immunity and flexible tuning.
FAQ
What is the maximum VCO center frequency achievable with 74HC7046AD,118?
The 74HC7046AD,118 achieves a typical VCO center frequency of 17 MHz at VCC = 4.5 V with R1 = 3 kΩ and C1 = 40 pF. Under optimal conditions (VCC = 6.0 V, minimal C1), the device supports up to 21 MHz. This performance is documented in the Philips 74HC/HCT7046A datasheet Figure 17 and Quick Reference Data table, confirming its suitability for VHF-band applications.
How does the DEMOUT pin (pin 10) function in 74HC7046AD,118?
The DEMOUT pin on the 74HC7046AD,118 provides a buffered, exact replica of the VCOIN voltage - unlike conventional demodulators that introduce a diode-drop offset. This eliminates calibration errors in analog filter designs and ensures the low-pass filter sees the true control voltage. When unused, DEMOUT must be left open; when used, a load resistor RS (50–300 kΩ) connects it to GND per datasheet Section "Demodulator section".
Can 74HC7046AD,118 operate with separate supply voltages for digital and VCO sections?
Yes, the 74HC7046AD,118 supports independent supply constraints: the digital section (phase comparators, lock detector) operates from 2.0–6.0 V, while the VCO section requires 3.0–6.0 V. This allows partial power-down - for example, holding VCC at 2.0 V disables the VCO while retaining digital logic state. The specification is explicitly defined in the "RECOMMENDED OPERATING CONDITIONS" table on page 9 of the Philips datasheet.
What is the functional difference between PC1 and PC2 in 74HC7046AD,118?
PC1 is an XOR phase comparator requiring 50% duty-cycle inputs and exhibiting harmonic locking (can lock to 2nd/3rd harmonics of fo); PC2 is an edge-triggered JK phase/frequency detector insensitive to duty cycle and providing zero static phase error across the full VCO range. Their transfer functions differ: PC1 yields VDEMOUT ∝ φSIGIN−φCOMPIN, while PC2 yields VDEMOUT ∝ (φSIGIN−φCOMPIN)/4π - detailed in Figures 6 and 8 of the datasheet.
How is lock detection implemented in 74HC7046AD,118?
Lock detection in the 74HC7046AD,118 uses an internal circuit that monitors phase error amplitude; when the PLL is locked, pin 1 (LD) outputs a HIGH level. A capacitor CLD must be connected between pin 15 (CLD) and pin 8 (GND) to set the lock detection time constant. The required CLD value is determined from Figure 32 in the datasheet and depends on loop bandwidth - typical values range from 1 nF to 10 nF for standard applications.
74HC7046AD,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Phase Lock Loop (PLL)
- PLL:
- Yes
- Input:
- Clock
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:3
- Differential - Input:Output:
- No/No
- Frequency - Max:
- 21MHz
- Divider/Multiplier:
- No/No
- Voltage - Supply:
- 3V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-SO
74HC7046AD,118 FAQ
1.How can I place an order for 74HC7046AD,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC7046AD,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC7046AD,118 reliable?
The price and inventory of 74HC7046AD,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC7046AD,118 is usually 5 days.
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74HC7046AD,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC7046AD,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC7046AD,118?
For technical support, including 74HC7046AD,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC7046AD,118 requirements.
6.How does Aetrix verify that 74HC7046AD,118 is sourced from the original manufacturer or authorized distributors?
All 74HC7046AD,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC7046AD,118 meets industry standards.
7.What is the process for return or replacement of 74HC7046AD,118?
All 74HC7046AD,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC7046AD,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC7046AD,118 part is unused and in its original packaging.
Return procedure for 74HC7046AD,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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