NXP Semiconductors 74HC7046ADB,118
- Part No.:
- 74HC7046ADB,118
- Manufacturer:
- NXP Semiconductors
- Package:
- 16-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74HC7046ADB,118.pdf
- Description:
- IC PHASE LOCK LOOP 16SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74HC7046ADB,118 from NXP Semiconductors is a high-speed Si-gate CMOS phase-locked-loop (PLL) IC with integrated lock detector, VCO, and dual phase comparators (XOR and edge-triggered JK). It delivers 17 MHz typical VCO center frequency at 4.5 V, 50% VCOOUT duty factor (±1%), and operates across 2.0–6.0 V digital supply and 3.0–6.0 V VCO supply. It is used in FM demodulation, tone decoding, and data synchronization circuits.
For engineers reviewing the 74HC7046ADB,118 datasheet, 74HC7046ADB,118 pinout, 74HC7046ADB,118 application, or 74HC7046ADB,118 equivalent, key selection criteria include VCO linearity (≤0.4% at 4.5 V), lock detector output (LD, pin 1), dual comparator selection (PC1OUT/PC2OUT), and external R/C tuning requirements for frequency range and offset control.
Technical Context
The 74HC7046ADB,118 integrates a linear voltage-controlled oscillator (VCO) with op-amp buffering for zero voltage offset, two independent phase comparators (PC1: XOR; PC2: edge-triggered JK flip-flop), and a dedicated lock detector (LD) that asserts HIGH when phase/frequency lock is achieved. Its VCO requires external R1/R2 and C1 components to set center frequency (fo), lock range (2fL), and optional frequency offset.
PC1 supports 50% duty-cycle input signals and provides ripple-suppressed average output proportional to phase difference (Kp = VCC/π); PC2 enables frequency acquisition without duty-cycle constraints and delivers 3-state output with inherent noise immunity. The DEMOUT pin (pin 10) replicates VCOIN voltage for low-pass filter monitoring without threshold drop.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCO center frequency | 17 MHz typical at VCC = 4.5 V, R1 = 3 kΩ, C1 = 40 pF - sets PLL operating band for FM/tone applications |
| VCO frequency linearity | 0.4% max at VCC = 4.5 V - ensures accurate voltage-to-frequency conversion and stable loop response |
| Duty factor (VCOOUT) | 50% ±1% at constant DC VCOIN - enables precise clock generation and symmetric waveform synthesis |
| Lock detector output | Active-HIGH LD (pin 1) - provides system-level lock status without external logic |
| Supply voltage range | Digital section: 2.0–6.0 V; VCO section: 3.0–6.0 V - allows mixed-voltage system integration |
| Phase comparator options | PC1 (XOR) for harmonic-locking & noise rejection; PC2 (edge-triggered JK) for frequency acquisition & low ripple |
| Input sensitivity (AC-coupled) | 15 mVp-p at 1 MHz - supports low-amplitude signal conditioning without pre-amplification |
Pinout & Package
74HC7046ADB,118 is housed in a 16-pin SO (Small Outline) package per JEDEC MS-012AA, with 1.27 mm pitch and gull-wing leads. Pin 8 is GND; pin 16 is VCC; pin 1 is LD (lock detect); pins 2 and 13 are PC1OUT and PC2OUT respectively; pins 6/7 are C1A/C1B for VCO capacitor connection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (LD) | Lock detector output | Open-drain HIGH when PLL achieves phase/frequency lock - drives status LED or microcontroller interrupt |
| 2 (PC1OUT) | Phase comparator 1 output | XOR-based error signal - feeds low-pass filter to VCOIN; requires external RC filtering for stability |
| 3 (COMPIN) | Comparator input | Reference signal input for phase comparison - accepts DC- or AC-coupled signals up to 17 MHz |
| 4 (VCOOUT) | VCO output | 50% duty-cycle square wave - directly usable as system clock or fed back via divider for frequency synthesis |
| 5 (INH) | VCO inhibit control | Active-HIGH disables VCO and DEMOUT - reduces standby current to ≤160 µA for power-sensitive designs |
| 6 (C1A), 7 (C1B) | VCO capacitor terminals | Differential connection for timing capacitor C1 - determines VCO frequency range and linearity |
| 9 (VCOIN) | VCO input control voltage | Analog voltage (1.1–4.9 V) setting instantaneous VCO frequency - buffered by internal op-amp |
| 10 (DEMOUT) | Demodulator output | Exact replica of VCOIN voltage - eliminates threshold drop for accurate filter monitoring and feedback |
| 11 (R1), 12 (R2) | VCO resistor connections | R1 sets base frequency; R2 adds programmable offset - parallel R1||R2 > 2.7 kΩ required for stability |
| 14 (SIGIN) | Signal input | Self-biasing amplifier input - accepts small-swing AC signals (≥15 mVp-p) or large DC-coupled logic signals |
| 15 (CLD) | Lock detector capacitor | Connects to GND (pin 8) to set lock detection time constant - value selected per Fig.32 for target response |
Key Features
| Feature | Design Value |
|---|---|
| Dual selectable phase comparators | PC1 (XOR) enables harmonic locking and high noise immunity; PC2 (JK) guarantees frequency capture without duty-cycle dependency |
| VCO-inhibit control (INH) | Reduces quiescent current to ≤160 µA in standby - critical for battery-powered tone decoders and motor controllers |
| Op-amp buffered VCOIN/DEMOUT | Zero voltage offset and matched DEMOUT = VCOIN - eliminates calibration drift and simplifies low-pass filter design |
| External R/C programmability | R1/R2 (3–300 kΩ) and C1 (>40 pF) allow full VCO center frequency (7–21 MHz) and offset tuning - no fixed-frequency limitation |
| Lock detector with CLD capacitor | Configurable lock response time via CLD capacitor (pin 15 to GND) - supports fast acquisition in data sync or slow settling in precision V/F conversion |
Applications
| FM Demodulation | Tone Decoding |
|---|---|
Use Scenario: Recovering audio from broadcast FM signals in consumer receivers or telemetry links. IC Role / Device Role / Timing Role: PLL acts as frequency discriminator - VCO tracks carrier deviation; DEMOUT voltage is proportional to instantaneous frequency. Use Value: 0.4% VCO linearity ensures <1% distortion in recovered audio; 17 MHz center frequency covers standard FM band (88–108 MHz) with prescaling. |
Use Scenario: Detecting DTMF or sub-audible tones in security systems, modems, or industrial controls. IC Role / Device Role / Timing Role: Configured as narrowband frequency tracker - SIGIN receives filtered tone; LD confirms lock to target frequency. Use Value: Dual comparator support allows PC2 for fast acquisition on tone onset and PC1 for stable tracking - reduces false triggers in noisy environments. |
| Data Synchronization | Motor-Speed Control |
Use Scenario: Aligning asynchronous serial data streams in legacy industrial networks or instrumentation buses. IC Role / Device Role / Timing Role: PLL recovers clock from NRZ data - VCOOUT regenerates clean bit clock; LD validates lock before enabling data sampling. Use Value: 15 mVp-p AC input sensitivity permits direct coupling to transformer-isolated RS-485 lines without amplification. |
Use Scenario: Closed-loop speed regulation of DC motors using back-EMF frequency feedback. IC Role / Device Role / Timing Role: VCO converts tachometer pulse frequency to analog control voltage (VCOIN); DEMOUT feeds motor driver's error amplifier. Use Value: 50% ±1% VCOOUT duty factor ensures balanced PWM drive; VCO linearity maintains linear speed vs. reference voltage relationship. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar phase-locked-loop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CD4046BE | CMOS-compatible but older technology; lower max VCO frequency (1.2 MHz typ. at 5 V); no dual comparator option - only XOR-type PC | Limited to low-frequency V/F conversion and basic tone detection; lacks PC2 for robust frequency acquisition | Select only for legacy designs where 17 MHz capability and harmonic rejection are unnecessary |
| SN74LV4046A | Lower voltage operation (1.65–5.5 V); improved propagation delay (19 ns typ.); same dual-comparator architecture but no DEMOUT pin | Better suited for 3.3 V embedded systems; missing DEMOUT requires external buffer for VCOIN monitoring | Prefer for new 3.3 V designs requiring faster response; avoid if DEMOUT-driven filter monitoring is required |
Compared with CD4046BE and SN74LV4046A, the 74HC7046ADB,118 uniquely combines 17 MHz VCO performance, dual comparator flexibility, and buffered DEMOUT for precision analog feedback - making it optimal for FM demodulation and high-fidelity tone decoding where linearity and lock reliability are critical.
Availability
74HC7046ADB,118 is available at Aetrix Electronics and suitable for FM demodulation, tone decoding, data synchronization, and motor-speed control applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for 74HC7046ADB,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in analog and mixed-signal IC design.
The 74HC7046ADB,118 belongs to NXP's legacy HC logic family and was engineered specifically for analog-intensive PLL applications - emphasizing VCO linearity, lock detection integrity, and flexible external tuning for communication and control systems.
FAQ
What is the maximum VCO center frequency achievable with 74HC7046ADB,118?
The 74HC7046ADB,118 achieves a typical VCO center frequency of 17 MHz at VCC = 4.5 V with R1 = 3 kΩ and C1 = 40 pF. Under optimized conditions (VCC = 6.0 V, minimal C1), the device supports up to 21 MHz. This makes the 74HC7046ADB,118 suitable for FM broadcast band applications when combined with prescaling, and for high-speed data recovery in legacy serial protocols.
How does the lock detector (LD) output function in 74HC7046ADB,118?
The LD pin (pin 1) of the 74HC7046ADB,118 asserts a HIGH-level signal when the PLL achieves stable phase and frequency lock between SIGIN and COMPIN. It requires an external capacitor (CLD) connected between pin 15 (CLD) and pin 8 (GND) to set detection time constant. The 74HC7046ADB,118 LD output is open-drain and must be pulled up externally to indicate lock status to microcontrollers or status indicators.
Can 74HC7046ADB,118 operate with separate supply voltages for digital and VCO sections?
Yes - the 74HC7046ADB,118 supports independent supply ranges: the digital section (phase comparators, lock detector) operates from 2.0 V to 6.0 V, while the VCO section requires 3.0 V to 6.0 V. This allows mixed-voltage system integration, such as using 3.3 V for logic interfacing and 5.0 V for higher VCO performance. The 74HC7046ADB,118 datasheet specifies distinct VIH/VIL thresholds for INH under each condition.
What is the purpose of the DEMOUT pin in 74HC7046ADB,118?
The DEMOUT pin (pin 10) of the 74HC7046ADB,118 provides an exact buffered replica of the VCOIN control voltage - unlike conventional PLLs where DEMOUT is offset by one threshold voltage. This zero-offset replication enables precise low-pass filter monitoring and direct feedback without calibration. When used, a load resistor (RS = 50–300 kΩ) must connect DEMOUT to GND; if unused, DEMOUT is left open.
How do PC1 and PC2 differ in functionality within 74HC7046ADB,118?
PC1 is an XOR phase comparator requiring 50% duty-cycle inputs and offering high noise immunity and harmonic locking; PC2 is an edge-triggered JK flip-flop comparator that acquires lock regardless of input duty cycle and produces low-ripple 3-state output. The 74HC7046ADB,118 allows hardware selection via external routing - PC1OUT (pin 2) and PC2OUT (pin 13) are independent outputs, enabling application-specific comparator choice without redesign.
74HC7046ADB,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74HC
- Package/Case:
- 16-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Phase Lock Loop (PLL)
- PLL:
- Yes
- Input:
- Clock
- Output:
- Clock
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:3
- Differential - Input:Output:
- No/No
- Frequency - Max:
- 21MHz
- Divider/Multiplier:
- No/No
- Voltage - Supply:
- 3V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-SSOP
74HC7046ADB,118 FAQ
1.How can I place an order for 74HC7046ADB,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC7046ADB,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC7046ADB,118 reliable?
The price and inventory of 74HC7046ADB,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC7046ADB,118 is usually 5 days.
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Once your 74HC7046ADB,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC7046ADB,118?
For technical support, including 74HC7046ADB,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC7046ADB,118 requirements.
6.How does Aetrix verify that 74HC7046ADB,118 is sourced from the original manufacturer or authorized distributors?
All 74HC7046ADB,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC7046ADB,118 meets industry standards.
7.What is the process for return or replacement of 74HC7046ADB,118?
All 74HC7046ADB,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC7046ADB,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC7046ADB,118 part is unused and in its original packaging.
Return procedure for 74HC7046ADB,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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