Nexperia USA Inc. 74HC73DB,112
- Part No.:
- 74HC73DB,112
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Flip Flops
- Package:
- 14-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
74HC73DB,112.pdf
- Description:
- IC FF JK TYPE DUAL 1BIT 14SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,071
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Product details
Overview
74HC73DB,112 from Nexperia is a dual negative-edge-triggered JK flip-flop with asynchronous reset, used for synchronous logic state storage and edge-sensitive control in digital sequencers, counters, and register files. It features two independent flip-flops, 2.0–6.0 V supply range, Schmitt-trigger clock inputs, and operation up to +125 °C.
For engineers reviewing the 74HC73DB,112 datasheet, 74HC73DB,112 pinout, 74HC73DB,112 application, or 74HC73DB,112 equivalent, this page delivers verified functional behavior, SO14 package mapping, timing constraints (e.g., 15 ns tpd at 6.0 V), reset propagation delay, and direct substitution guidance for legacy 74HC73 variants.
Technical Context
This device implements two independent JK flip-flops sharing no internal coupling-each has dedicated J, K, nCP (negative-edge clock), and nR (asynchronous active-low reset) terminals. The Schmitt-trigger input on each nCP enables robust operation with slow-rising or noisy clock signals, eliminating external hysteresis circuitry.
Each flip-flop provides complementary true (nQ) and inverted (nQ) outputs, supports toggle/set/reset/hold modes per the function table, and guarantees predictable state transitions only when J/K inputs meet setup time (e.g., 14 ns min at 6.0 V) before the HIGH-to-LOW clock edge.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | 74HC high-speed CMOS - ensures low static current (≤80 μA at 6.0 V) and compatibility with TTL input thresholds |
| Supply Voltage Range | 2.0 V to 6.0 V - supports mixed-voltage system interfacing and battery-powered operation down to 2 V |
| Max Clock Frequency | 83 MHz at 6.0 V - enables use in high-speed control loops and data sampling up to 12 ns minimum clock period |
| Propagation Delay (nCP → nQ) | 15 ns typical at 6.0 V, CL = 50 pF - defines minimum state update latency for real-time sequencing |
| Reset Propagation Delay (nR → nQ) | 14 ns typical at 6.0 V - ensures rapid forced state clearance critical in fault-recovery circuits |
| Input Setup Time (nJ/nK → nCP) | 3 ns minimum at 6.0 V - constrains maximum data path delay before clock edge for reliable latching |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor drives |
Pinout & Package
74HC73DB,112 is supplied in SO14 (SOT108-1) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 5 (1CP, 2CP) | Clock input (negative-edge triggered) | Triggers state update on HIGH-to-LOW transition; Schmitt-trigger input rejects noise below hysteresis threshold |
| 2, 6 (1R, 2R) | Asynchronous reset (active LOW) | Forces nQ = LOW / nQ = HIGH immediately, overriding clock and data - used for power-on initialization or fault shutdown |
| 3, 10 (1K, 2K) | Synchronous K input | Controls reset action during clocked operation; must be stable ≥tsu before nCP edge |
| 4 | Positive supply (VCC) | Primary power rail; decoupling capacitor required within 10 mm for stable switching performance |
| 7, 14 (2J, 1J) | Synchronous J input | Controls set action during clocked operation; paired with K to define toggle/set/reset/hold behavior |
| 8, 13 (2Q, 1Q) | Inverted output (nQ) | Complementary to true output; enables direct connection to enable/disable logic without external inverters |
| 9, 12 (2Q, 1Q) | True output (nQ) | Primary state output; fan-out limited to 10 LS-TTL loads or 1 HC/HCT load at 6.0 V |
| 11 | Ground (GND) | Reference return path; requires low-inductance connection to minimize ground bounce during simultaneous switching |
Key Features
| Feature | Design Value |
|---|---|
| CMOS low-power dissipation | ICC ≤ 4.0 μA typical at 6.0 V - extends battery life in portable instrumentation and reduces thermal load in dense PCB layouts |
| Wide supply voltage range | 2.0 V to 6.0 V - eliminates level-shifting between 3.3 V microcontrollers and 5 V legacy peripherals |
| Schmitt-trigger clock inputs | Hysteresis ≥ 0.5 V at 4.5 V - allows direct connection to mechanical switches, RC oscillators, or unterminated traces without added debouncing |
| Asynchronous reset override | nR asserts independently of clock edge - enables deterministic system-wide reset in safety-critical control states |
| High noise immunity | VIL = 1.8 V / VIH = 4.2 V at 6.0 V - rejects >30 % supply noise on control lines, reducing false triggering in EMI-prone environments |
Applications
| Industrial PLC Counter Module | Digital Power Supply Sequencer |
|---|---|
Use Scenario: Counting encoder pulses in motor feedback loops while maintaining position state across power cycles. IC Role / Device Role / Timing Role: Dual JK flip-flop stores quadrature phase A/B edge counts; asynchronous reset clears count on emergency stop signal. Use Value: Negative-edge triggering synchronizes cleanly with encoder falling edges; 125 °C rating supports placement near heatsinks in compact power modules. |
Use Scenario: Controlling startup sequence of multi-rail DC-DC converters (12 V → 5 V → 3.3 V → 1.8 V) with interlocked enable signals. IC Role / Device Role / Timing Role: Each flip-flop holds enable state for one rail; J/K inputs configure dependency logic (e.g., 5 V must be stable before enabling 3.3 V). Use Value: Complementary outputs drive both high-side and low-side enable paths; wide VCC range accommodates monitoring of 12 V rail directly. |
| Automotive Body Control Unit | Test Equipment Pattern Generator |
Use Scenario: Debouncing door lock/unlock switch inputs and storing actuator command state in CAN gateway modules. IC Role / Device Role / Timing Role: One flip-flop latches lock command; second stores unlock status; nR tied to watchdog timeout signal. Use Value: Schmitt-trigger nCP accepts noisy switch signals without external RC filters; -40 °C to +125 °C rating meets AEC-Q100 ambient requirements. |
Use Scenario: Generating precise, repeatable test vectors for digital ASIC validation using programmable state machines. IC Role / Device Role / Timing Role: Flip-flops implement 2-bit counter stages; J/K inputs driven by FPGA GPIO to reconfigure pattern length and sequence. Use Value: 15 ns propagation delay enables 66 MHz pattern rates; SO14 package allows dense routing on high-speed probe cards. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual JK flip-flop with reset applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC73DR | TI SO14 variant; identical AC/DC specs but different ESD ratings (HBM 4 kV vs. Nexperia's 2 kV) | Valid for industrial designs requiring TI-qualified supply chain; not automotive-qualified | Select if TI sourcing preference exists and HBM >2 kV is required |
| 74HCT73DB,112 | TTL-compatible input thresholds (VIH = 2.0 V min); otherwise identical pinout, timing, and packaging | Required when interfacing with legacy 5 V TTL logic families without level shifters | Choose only when driving from 5 V TTL outputs; otherwise 74HC73DB,112 offers lower power |
Compared with SN74HC73DR and 74HCT73DB,112, the 74HC73DB,112 provides optimal balance of low ICC (4 μA), Schmitt-trigger noise immunity, and broad VCC range - making it preferred for new designs with mixed-voltage interfaces and battery-sensitive operation.
Availability
74HC73DB,112 is available at Aetrix Electronics and suitable for industrial automation controllers, automotive body electronics, and test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74HC73DB,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET devices optimized for efficiency and miniaturization in high-volume applications.
The 74HC73 belongs to Nexperia's 74HC logic family - engineered for low-power, wide-VCC operation in industrial control, consumer electronics, and automotive subsystems where noise immunity and thermal stability are critical.
FAQ
What is the minimum setup time required for J and K inputs relative to the clock edge?
The 74HC73DB,112 requires J and K inputs to be stable for at least 3 ns before the HIGH-to-LOW clock transition at VCC = 6.0 V, per Table 7. This value increases to 14 ns at VCC = 2.0 V. Violating setup time risks metastability or incorrect state capture, especially in high-noise environments.
Can the asynchronous reset (nR) be used while the clock is held HIGH?
Yes - nR is fully asynchronous and operates independently of the clock state. When nR is pulled LOW, nQ forces to LOW and nQ to HIGH immediately, regardless of nCP level or timing. This behavior is guaranteed across the full -40 °C to +125 °C operating range and does not require clock activity.
Does the 74HC73DB,112 support mixed-voltage operation between inputs and outputs?
No - all inputs and outputs reference the same VCC rail. Input thresholds scale with VCC (e.g., VIH = 4.2 V at 6.0 V), and outputs swing rail-to-rail. Interfacing with lower-voltage logic requires external level shifters or series resistors with clamping diodes, as enabled by the built-in input clamp diodes.
Is the SO14 package (SOT108-1) RoHS-compliant and lead-free?
Yes - the 74HC73DB,112 uses a lead-free, RoHS-compliant SO14 package (SOT108-1) with matte tin-plated gull-wing leads. Reflow profile follows JEDEC J-STD-020D, with peak temperature ≤ 260 °C and time above liquidus ≤ 60 seconds, ensuring compatibility with standard Pb-free assembly processes.
74HC73DB,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74HC
- Package/Case:
- 14-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Function:
- Reset
- Type:
- JK Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 83 MHz
- Max Propagation Delay @ V, Max CL:
- 27ns @ 6V, 50pF
- Trigger Type:
- Negative Edge
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 3.5 pF
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SSOP
74HC73DB,112 FAQ
1.How can I place an order for 74HC73DB,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74HC73DB,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74HC73DB,112 reliable?
The price and inventory of 74HC73DB,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74HC73DB,112 is usually 5 days.
3.What payment methods are accepted for 74HC73DB,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74HC73DB,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74HC73DB,112?
74HC73DB,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74HC73DB,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74HC73DB,112?
For technical support, including 74HC73DB,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74HC73DB,112 requirements.
6.How does Aetrix verify that 74HC73DB,112 is sourced from the original manufacturer or authorized distributors?
All 74HC73DB,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74HC73DB,112 meets industry standards.
7.What is the process for return or replacement of 74HC73DB,112?
All 74HC73DB,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74HC73DB,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74HC73DB,112 part is unused and in its original packaging.
Return procedure for 74HC73DB,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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